📄 startup.s
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;******************************************************************************
;*
;* System On Chip(SOC)
;*
;* Copyright (c) 2002 Software Center, Samsung Electronics, Inc.
;* Copyright (c) 2002 Mobile Solution Project Team, Samsung Electronics, Inc.
;* All rights reserved.
;*
;* This software is the confidential and proprietary information of Samsung
;* Electronics, Inc("Confidential Information"). You Shall not disclose such
;* Confidential Information and shall use it only in accordance with the terms
;* of the license agreement you entered into Samsung.
;*
;******************************************************************************
OPT 2
INCLUDE kxarm.h
INCLUDE armmacros.s
INCLUDE s3c2440x.inc
OPT 1
OPT 128
;---------------------------------------------------------------------------
; 4 LED light function
; The LEDs are located below AMD Flash ROM
MACRO
LED_ON $data
LDR r10, =0x56000054
LDR r11, =$data
MOV r11, r11, lsl #4
STR r11, [r10]
MEND
;---------------------------------------------------------------------------
; 4 LED light function
; The LEDs are located below AMD Flash ROM
MACRO
VLED_ON $data
LDR r10, =0xB1600054
LDR r11, =$data
MOV r11, r11, lsl #4
STR r11, [r10]
MEND
;---------------------------------------------------------------------------
IMPORT KernelStart
IMPORT OALClearUTLB
IMPORT OALFlushICache
IMPORT OALFlushDCache
EXPORT SelfRefreshAndPowerOff
; Data Cache Characteristics.
;
DCACHE_LINES_PER_SET_BITS EQU 6
DCACHE_LINES_PER_SET EQU 64
DCACHE_NUM_SETS EQU 8
DCACHE_SET_INDEX_BIT EQU (32 - DCACHE_LINES_PER_SET_BITS)
DCACHE_LINE_SIZE EQU 32
SLEEPDATA_BASE_VIRTUAL EQU 0xA0020800 ; keep in sync w/ config.bib
SLEEPDATA_BASE_PHYSICAL EQU 0x30020800
SleepState_Data_Start EQU (0)
SleepState_WakeAddr EQU (SleepState_Data_Start )
SleepState_MMUCTL EQU (SleepState_WakeAddr + WORD_SIZE )
SleepState_MMUTTB EQU (SleepState_MMUCTL + WORD_SIZE )
SleepState_MMUDOMAIN EQU (SleepState_MMUTTB + WORD_SIZE )
SleepState_SVC_SP EQU (SleepState_MMUDOMAIN + WORD_SIZE )
SleepState_SVC_SPSR EQU (SleepState_SVC_SP + WORD_SIZE )
SleepState_FIQ_SPSR EQU (SleepState_SVC_SPSR + WORD_SIZE )
SleepState_FIQ_R8 EQU (SleepState_FIQ_SPSR + WORD_SIZE )
SleepState_FIQ_R9 EQU (SleepState_FIQ_R8 + WORD_SIZE )
SleepState_FIQ_R10 EQU (SleepState_FIQ_R9 + WORD_SIZE )
SleepState_FIQ_R11 EQU (SleepState_FIQ_R10 + WORD_SIZE )
SleepState_FIQ_R12 EQU (SleepState_FIQ_R11 + WORD_SIZE )
SleepState_FIQ_SP EQU (SleepState_FIQ_R12 + WORD_SIZE )
SleepState_FIQ_LR EQU (SleepState_FIQ_SP + WORD_SIZE )
SleepState_ABT_SPSR EQU (SleepState_FIQ_LR + WORD_SIZE )
SleepState_ABT_SP EQU (SleepState_ABT_SPSR + WORD_SIZE )
SleepState_ABT_LR EQU (SleepState_ABT_SP + WORD_SIZE )
SleepState_IRQ_SPSR EQU (SleepState_ABT_LR + WORD_SIZE )
SleepState_IRQ_SP EQU (SleepState_IRQ_SPSR + WORD_SIZE )
SleepState_IRQ_LR EQU (SleepState_IRQ_SP + WORD_SIZE )
SleepState_UND_SPSR EQU (SleepState_IRQ_LR + WORD_SIZE )
SleepState_UND_SP EQU (SleepState_UND_SPSR + WORD_SIZE )
SleepState_UND_LR EQU (SleepState_UND_SP + WORD_SIZE )
SleepState_SYS_SP EQU (SleepState_UND_LR + WORD_SIZE )
SleepState_SYS_LR EQU (SleepState_SYS_SP + WORD_SIZE )
SleepState_Data_End EQU (SleepState_SYS_LR + WORD_SIZE )
SLEEPDATA_SIZE EQU (SleepState_Data_End - SleepState_Data_Start) / 4
BIT_SELFREFRESH EQU (1<<22)
HandleFIQ EQU 0x33ffff1c
;**
; * StartUp - Image EntryPoint
; *
; * @return .
; * @param .
; *
STARTUPTEXT
LEAF_ENTRY StartUp
1 b ResetHandler
b %B1 ;handler for Undefined mode
b %B1 ;handler for SWI interrupt
b %B1 ;handler for PAbort
b %B1 ;handler for DAbort
b %B1 ;reserved
b %B1 ;handler for IRQ interrupt
b ENTER_POWER_OFF ;handler for FIQ interrupt
SelfRefreshAndPowerOff ; run with Instruction Cache's code
str r1, [r0] ; Enable SDRAM self-refresh
str r3, [r2] ; MISCCR Setting
str r5, [r4] ; Power Off !!
b .
ENTER_POWER_OFF ;FIQ Handler
; LED_ON 0x4
ldr r0,=GPFCON
ldr r1,=0x5500
str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0x20
str r1,[r0]
ldr r5,=REFRESH
ldr r6,[r5]
orr r6, r6, #BIT_SELFREFRESH
ldr r3,=MISCCR
ldr r4,[r3]
orr r4,r4,#(3<<17)
bic r4,r4, #(7 << 20)
orr r4,r4, #(6 << 20)
ldr r2,=0x7fff8
ldr r1,=CLKCON
mov r0,#16
b _EPO ;This code isn't needed for code on the ROM
ALIGN 32
_EPO
1 str r6, [r5] ;Enable SDRAM self-refresh
2 subs r0,r0,#1 ;Wait until self-refresh is issued,which may not be needed.
bne %B2
str r4,[r3] ;Make sure that SCLK0:SCLK->0, SCLK1:SCLK->0, SCKE=L during boot-up
str r2,[r1] ;CPU will enter into POWER_OFF mode.
b .
LTORG
ResetHandler
ldr r0, = INTMSK
ldr r1, = ~BIT_BAT_FLT ; all interrupt disable, nBATT_FLT =enabled
str r1, [r0]
ldr r0, = INTSUBMSK
ldr r1, = 0x7ff ;all sub interrupt disable
str r1, [r0]
ldr r0, = INTMOD
ldr r1, = BIT_BAT_FLT ; set all interrupt as IRQ, BAT_FLT = FIQ
str r1, [r0]
ldr r1, =MISCCR ; MISCCR's Bit [22:20] -> 100
ldr r0, [r1]
bic r0, r0, #(7 << 20)
orr r0, r0, #(4 << 20)
str r0, [r1]
[{FALSE}
bl OALClearUTLB
bl OALFlushICache
ldr r0, = (DCACHE_LINES_PER_SET - 1)
ldr r1, = (DCACHE_NUM_SETS - 1)
ldr r2, = DCACHE_SET_INDEX_BIT
ldr r3, = DCACHE_LINE_SIZE
bl OALFlushDCache
nop
nop
nop
]
ldr r0, = GPFCON
ldr r1, = 0x55aa
str r1, [r0]
ldr r0, = WTCON ; watch dog disable
ldr r1, = 0x0
str r1, [r0]
[ {FALSE}
ldr r0, = CLKDIVN
ldr r1, = CLKDIVVAL
str r1, [r0]
ands r1, r1, #0xe ; Make AsyncBusMode
beq %F1
]
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #R1_nF:OR:R1_iA
mcr p15, 0, r0, c1, c0, 0
1
mov r0, #0x2000
2
subs r0, r0, #1
bne %B2
; :::::::::::::::::::::::::::::::::::::::::::::
; Add for Power Management
; - - - - - - - - - - - - - - - - - - - - - - -
ldr r1, =GSTATUS2 ; Determine Booting Mode
ldr r10, [r1]
tst r10, #0x2 ; Power-Off reset Check
beq %F4
; Case of Power-off reset
3
ldr r1, =MISCCR ; MISCCR's Bit 17, 18, 19 -> 0
ldr r0, [r1]
bic r0, r0, #(3 << 17)
str r0, [r1]
4
tst r10, #0x2 ; Power-Off reset check
beq BringUpWinCE ; Normal Mode Booting
; Recover Process : Starting Point
ldr r1, =GSTATUS2 ; Determine Booting Mode
ldr r10, [r1]
str r10, [r1] ; Clear Booting Mode
; 1. Checksum Calculation saved Data
ldr r5, =SLEEPDATA_BASE_PHYSICAL ; pointer to physical address of reserved Sleep mode info data structure
mov r3, r5 ; pointer for checksum calculation
mov r2, #0
ldr r0, =SLEEPDATA_SIZE ; get size of data structure to do checksum on
40
ldr r1, [r3], #4 ; pointer to SLEEPDATA
and r1, r1, #0x1
mov r1, r1, LSL #31
orr r1, r1, r1, LSR #1
add r2, r2, r1
subs r0, r0, #1 ; dec the count
bne %b40 ; loop till done
ldr r0,=GSTATUS3
ldr r3, [r0] ; get the Sleep data checksum from the Power Manager Scratch pad register
teq r2, r3 ; compare to what we saved before going to sleep
bne JumpToRAM ; bad news - do a cold boot - If emergency power off case, normal booting.
b MMUENABLE
JumpToRAM
ldr r2, =0x201000 ; offset into the RAM
ldr r3, =0x30000000 ; add physical base
add r2, r2, r3
mov pc, r2 ; & jump to StartUp address
MMUENABLE
; 2. MMU Enable
ldr r10, [r5, #SleepState_MMUDOMAIN] ; load the MMU domain access info
ldr r9, [r5, #SleepState_MMUTTB] ; load the MMU TTB info
ldr r8, [r5, #SleepState_MMUCTL] ; load the MMU control info
ldr r7, [r5, #SleepState_WakeAddr] ; load the LR address
nop
nop
nop
nop
nop
; if software reset
mov r1, #0x38000000
teq r1, r7
bne %f1
bl BringUpWinCE
; wakeup routine
1
mcr p15, 0, r10, c3, c0, 0 ; setup access to domain 0
mcr p15, 0, r9, c2, c0, 0 ; PT address
mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs
mcr p15, 0, r8, c1, c0, 0 ; restore MMU control
; 3. Jump to Kernel Image's fw.s(Awake_address)
mov pc, r7 ; & jump to new virtual address (back up Power management stack)
nop
; - - - - - - - - - - - - - - - - - - - - - - -
; Add for Power Management
; :::::::::::::::::::::::::::::::::::::::::::::
BringUpWinCE
ldr r0, = GPFDAT
mov r1, #0x80
str r1, [r0]
add r0, pc, #g_oalAddressTable - (. + 8)
bl KernelStart
LTORG
INCLUDE oemaddrtab_cfg.inc
TEXTAREA
;**
; * CPUPowerWDReset - Software reset routine. Use watchdog timer and SDRAM to self-refresh mode.
; *
; * Entry none
; * Exit none
; * Uses r0-r3
; *
LEAF_ENTRY CPUPowerWDReset
; VLED_ON 0xb
;Watchdog reset enable.
ldr r1, =vWTCON
ldr r0, [r1]
orr r0, r0, #(1<<5) ; Enable watchdog timer.
str r0, [r1]
ldr r0, =vREFRESH
ldr r1, [r0] ; r1=rREFRESH
orr r1, r1, #(1 << 22)
;Set memory control self-refersh
ldr r0,=vREFRESH
ldr r3,[r0] ;r3=rREFRESH, may fill TLB
orr r3, r3, #BIT_SELFREFRESH
b %F1
ALIGN 32 ;The following instructions will be in I-Cache
1
str r3, [r0] ;Enable SDRAM self-refresh
b .
;**
; * CPUPowerReset - Software reset routine. Just jump to StartUp in this file.
; *
; * Entry none
; * Exit none
; * Uses r0-r3
; *
LEAF_ENTRY CPUPowerReset
ldr r3, =SLEEPDATA_BASE_VIRTUAL ; base of Sleep mode storage
mov r2, #0x38000000 ; store Virtual return address
str r2, [r3], #4
; Disable MMU
ldr r2, = PhysicalStart
ldr r3, = (0x80000000 - 0x30000000)
sub r2, r2, r3
mov r1, #0x0070 ; Disable MMU
mcr p15, 0, r1, c1, c0, 0
nop
mov pc, r2 ; Jump to PStart
nop
; MMU & caches now disabled.
PhysicalStart
bl OALClearUTLB
bl OALFlushICache
ldr r0, = (DCACHE_LINES_PER_SET - 1)
ldr r1, = (DCACHE_NUM_SETS - 1)
ldr r2, = DCACHE_SET_INDEX_BIT
ldr r3, = DCACHE_LINE_SIZE
bl OALFlushDCache
ldr r2, =0x201000 ; offset into the RAM
ldr r3, =0x30000000 ; add physical base
add r2, r2, r3
mov pc, r2 ; & jump to StartUp address
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