📄 fmd.cpp
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}
if(SI.bBadBlock != 0xFF)
{
dwResult |= BLOCK_STATUS_BAD;
}
return dwResult;
}
// FMD_EraseBlock
//
// Erase the given block
//
BOOL FMD_SB_EraseBlock(BLOCK_ID blockID, int mode)
{
BOOL bRet = TRUE;
DWORD dwPageID = blockID << SB_NAND_LOG_2_PAGES_PER_BLOCK;
// RETAILMSG(1, (TEXT("FMD::FMD_SB_EraseBlock 0x%x \r\n"), dwPageID));
BOOL bLastMode = SetKMode(TRUE);
// Enable the chip
SetChipSelect(mode,LOW);
NF_CLEAR_RB();
// Issue command
NF_CMD(CMD_ERASE);
// Set up address
NF_ADDR((dwPageID) & 0xff);
NF_ADDR((dwPageID >> 8) & 0xff);
if (SB_NEED_EXT_ADDR) {
NF_ADDR((dwPageID >> 16) & 0xff);
}
// Complete erase operation
NF_CMD(CMD_ERASE2);
// Wait for ready bit
NF_DETECT_RB(); // Wait tR(max 12us)
if ( READ_REGISTER_USHORT(pNFSTAT) & STATUS_ILLACC )
{
RETAILMSG(1, (TEXT("SB######## Error Erasing block (Illigar Access) %d!\n"), blockID));
WRITE_REGISTER_USHORT(pNFSTAT, STATUS_ILLACC); // Write 1 to clear.
bRet = FALSE;
}
else
{
// Check the status
NF_CMD(CMD_STATUS);
if(NF_DATA_R() & STATUS_ERROR) {
RETAILMSG(1, (TEXT("SB######## Error Erasing block %d!\n"), blockID));
bRet = FALSE;
}
}
SetChipSelect(mode,HIGH);
SetKMode(bLastMode);
return bRet;
}
// FMD_SB_WriteSector
//
// Write dwNumPages pages to the startSectorAddr
//
BOOL FMD_SB_WriteSector(SECTOR_ADDR startSectorAddr, LPBYTE pSectorBuff, PSectorInfo pSectorInfoBuff,
DWORD dwNumSectors, int mode)
{
DWORD i;
BOOL bRet = TRUE;
DWORD dwECCVal;
BYTE eccBuf[4];
// RETAILMSG(1, (TEXT("FMD::FMD_SB_WriteSector 0x%x \r\n"), startSectorAddr));
// Sanity check
// BUGBUGBUG: I need to come back to support dwNumSectors > 1
//
if((!pSectorBuff && !pSectorInfoBuff) || dwNumSectors != 1) {
RETAILMSG(1, (TEXT("Invalid parameters!\n")));
return FALSE;
}
if(!pSectorBuff) {
// If we are asked just to write the SectorInfo, we will do that separately
bRet = NAND_SB_WriteSectorInfo(startSectorAddr, pSectorInfoBuff, mode);
return bRet; // Do not write the actual sector information...
}
BOOL bLastMode = SetKMode(TRUE);
// Initialize ECC register
NF_RSTECC();
NF_MECC_UnLock();
// Enable Chip
SetChipSelect(mode,LOW);
// Issue command
NF_CMD(CMD_READ);
NF_CMD(CMD_WRITE);
// Setup address
NF_ADDR(0x00);
NF_ADDR((startSectorAddr) & 0xff);
NF_ADDR((startSectorAddr >> 8) & 0xff);
if (SB_NEED_EXT_ADDR) {
NF_ADDR((startSectorAddr >> 16) & 0xff);
}
// Special case to handle un-aligned buffer pointer.
//
if( ((DWORD) pSectorBuff) & 0x3) {
// Write the data
for(i=0; i<SECTOR_SIZE; i++) {
NF_DATA_W(pSectorBuff[i]);
}
}
else {
WritePage512(pSectorBuff, pNFDATA);
}
// Read out the ECC value generated by HW
NF_MECC_Lock();
dwECCVal = NF_ECC();
// Write the SectorInfo data to the media
// NOTE: This hardware is odd: only a byte can be written at a time and it must reside in the
// upper byte of a USHORT.
if(pSectorInfoBuff)
{
// Write the first reserved field (DWORD)
NF_DATA_W4(pSectorInfoBuff->dwReserved1);
// Write OEM reserved flag
NF_DATA_W( (pSectorInfoBuff->bOEMReserved) );
// Write the bad block flag
NF_DATA_W( (pSectorInfoBuff->bBadBlock) );
// Write the second reserved field
NF_DATA_W( (pSectorInfoBuff->wReserved2 >> 8) & 0xff );
NF_DATA_W( (pSectorInfoBuff->wReserved2) & 0xff );
}else
{
// Make sure we advance the Flash's write pointer (even though we aren't writing the SectorInfo data)
for(i=0; i<sizeof(SectorInfo); i++)
{
NF_DATA_W(0xff);
}
}
// ECC stuff should be here
eccBuf[0] = (BYTE) ((dwECCVal) & 0xff);
eccBuf[1] = (BYTE) ((dwECCVal >> 8) & 0xff);
eccBuf[2] = (BYTE) ((dwECCVal >> 16) & 0xff);
// Write the ECC value to the flash
for(i=0; i<3; i++) {
NF_DATA_W(eccBuf[i]);
}
for(i=0; i<5; i++) {
NF_DATA_W(0xff);
}
NF_CLEAR_RB();
// Finish up the write operation
NF_CMD(CMD_WRITE2);
// Wait for RB
NF_DETECT_RB(); // Wait tR(max 12us)
if ( READ_REGISTER_USHORT(pNFSTAT) & STATUS_ILLACC )
{
RETAILMSG(1, (TEXT("FMD_WriteSector() ######## Error Programming page (Illigar Access) %d!\n"), startSectorAddr));
WRITE_REGISTER_USHORT(pNFSTAT, STATUS_ILLACC); // Write 1 to clear.
bRet = FALSE;
}
else
{
// Check the status
NF_CMD(CMD_STATUS);
if(NF_DATA_R() & STATUS_ERROR) {
RETAILMSG(1, (TEXT("FMD_WriteSector() ######## Error Programming page %d!\n"), startSectorAddr));
bRet = FALSE;
}
}
// Disable the chip
SetChipSelect(mode,HIGH);
SetKMode(bLastMode);
return bRet;
}
/*
* MarkBlockBad
*
* Mark the block as a bad block. We need to write a 00 to the 517th byte
*/
BOOL SB_MarkBlockBad(BLOCK_ID blockID, int mode)
{
DWORD dwStartPage = blockID << SB_NAND_LOG_2_PAGES_PER_BLOCK;
BOOL bRet = TRUE;
RETAILMSG(1, (TEXT("SB_MarkBlockBad 0x%x \r\n"), dwStartPage));
BOOL bLastMode = SetKMode(TRUE);
// Enable chip
SetChipSelect(mode,LOW);
NF_CLEAR_RB();
// Issue command
// We are dealing with spare area
NF_CMD(CMD_READ2);
NF_CMD(CMD_WRITE);
// Set up address
NF_ADDR(VALIDADDR);
NF_ADDR((dwStartPage) & 0xff);
NF_ADDR((dwStartPage >> 8) & 0xff);
if (SB_NEED_EXT_ADDR) {
NF_ADDR((dwStartPage >> 16) & 0xff);
}
NF_DATA_W(BADBLOCKMARK);
// Copmlete the write
NF_CMD(CMD_WRITE2);
// Wait for RB
NF_DETECT_RB(); // Wait tR(max 12us)
if ( READ_REGISTER_USHORT(pNFSTAT) & STATUS_ILLACC )
{
RETAILMSG(1, (TEXT("######## Failed to mark the block bad (Illigar Access) ! %d \n"), blockID));
WRITE_REGISTER_USHORT(pNFSTAT, STATUS_ILLACC); // Write 1 to clear.
bRet = FALSE;
}
else
{
// Get the status
NF_CMD(CMD_STATUS);
if(NF_DATA_R() & STATUS_ERROR) {
RETAILMSG(1, (TEXT("######## Failed to mark the block bad!\n")));
bRet = FALSE;
}
}
// Disable chip select
SetChipSelect(mode,HIGH);
SetKMode(bLastMode);
return bRet;
}
//
// FMD_SB_SetBlockStatus
//
// Sets the status of a block. Only implement for bad blocks for now.
// Returns TRUE if no errors in setting.
//
BOOL FMD_SB_SetBlockStatus(BLOCK_ID blockID, DWORD dwStatus, int mode)
{
SECTOR_ADDR sectorAddr = blockID << SB_NAND_LOG_2_PAGES_PER_BLOCK;
BYTE bStatus = 0;
if(dwStatus & BLOCK_STATUS_BAD)
{
if(!SB_MarkBlockBad (blockID, mode))
{
return FALSE;
}
}
// We don't currently support setting a block to read-only, so fail if request is
// for read-only and block is not currently read-only.
if(dwStatus & BLOCK_STATUS_READONLY)
{
if(!(FMD_SB_GetBlockStatus(blockID, mode) & BLOCK_STATUS_READONLY))
{
return FALSE;
}
}
return TRUE;
}
//------------------------------- Private Interface (NOT used by the FAL) --------------------------
// FMD_SB_GetOEMReservedByte
//
// Retrieves the OEM reserved byte (for metadata) for the specified physical sector.
//
//
BOOL FMD_SB_GetOEMReservedByte(SECTOR_ADDR physicalSectorAddr, PBYTE pOEMReserved, int mode)
{
BOOL bLastMode = SetKMode(TRUE);
// Enable chip select
SetChipSelect(mode,LOW);
NF_CLEAR_RB();
// Issue command
NF_CMD(CMD_READ2);
// Set up address
NF_ADDR(OEMADDR);
NF_ADDR((physicalSectorAddr) & 0xff);
NF_ADDR((physicalSectorAddr >> 8) & 0xff);
if (SB_NEED_EXT_ADDR) {
NF_ADDR((physicalSectorAddr >> 16) & 0xff);
}
// Wait for the ready bit
NF_DETECT_RB(); // Wait tR(max 12us)
// Read the data
*pOEMReserved = (BYTE) NF_DATA_R();
// Disable chip select
SetChipSelect(mode,HIGH);
SetKMode(bLastMode);
return TRUE;
}
// FMD_SB_SetOEMReservedByte
//
// Sets the OEM reserved byte (for metadata) for the specified physical sector.
//
BOOL FMD_SB_SetOEMReservedByte(SECTOR_ADDR physicalSectorAddr, BYTE bOEMReserved, int mode)
{
BOOL bRet = TRUE;
BOOL bLastMode = SetKMode(TRUE);
// Enable chip select
SetChipSelect(mode,LOW);
NF_CLEAR_RB();
// Issue command
NF_CMD(CMD_READ2);
NF_CMD(CMD_WRITE);
// Set up address
NF_ADDR(OEMADDR);
NF_ADDR((physicalSectorAddr) & 0xff);
NF_ADDR((physicalSectorAddr >> 8) & 0xff);
if (SB_NEED_EXT_ADDR) {
NF_ADDR((physicalSectorAddr >> 16) & 0xff);
}
// Write the data
NF_DATA_W(bOEMReserved);
// Complete the write
NF_CMD(CMD_WRITE2);
// Wait for the ready bit
NF_DETECT_RB(); // Wait tR(max 12us)
if ( READ_REGISTER_USHORT(pNFSTAT) & STATUS_ILLACC )
{
RETAILMSG(1, (TEXT("######## Failed to set OEM Reserved byte (Illigar Access) ! %d \n"), physicalSectorAddr));
WRITE_REGISTER_USHORT(pNFSTAT, STATUS_ILLACC); // Write 1 to clear.
bRet = FALSE;
}
else
{
// Read the status
NF_CMD(CMD_STATUS);
// Check the status
if(NF_DATA_R() & STATUS_ERROR) {
RETAILMSG(1, (TEXT("######## Failed to set OEM Reserved byte!\n")));
bRet = FALSE;
}
}
// Disable chip select
SetChipSelect(mode,HIGH);
SetKMode(bLastMode);
return bRet;
}
// Reset the chip
//
void LB_NF_Reset(int mode)
{
int i;
SetChipSelect(mode,LOW);
NF_CLEAR_RB();
NF_CMD(CMD_RESET);
for(i=0;i<10;i++); //tWB = 100ns. //??????
SetChipSelect(mode,HIGH);
}
/*
* NAND_LB_ReadSectorInfo
*
* Read SectorInfo out of the spare area. The current implementation only handles
* one sector at a time.
*/
void NAND_LB_ReadSectorInfo(SECTOR_ADDR sectorAddr, PSectorInfo pInfo, int mode)
{
volatile DWORD rddata;
int NewSpareAddr = 2048 + 16*(sectorAddr%4);
int NewSectorAddr = sectorAddr/4;
// RETAILMSG(1, (TEXT("FMD::NAND_LB_ReadSectorInfo 0x%x \r\n"), sectorAddr));
BOOL bLastMode = SetKMode(TRUE);
// Chip enable
SetChipSelect(mode,LOW);
NF_CLEAR_RB();
// Write the command
NF_CMD(CMD_READ);
// Write the address
NF_ADDR((NewSpareAddr)&0xff);
NF_ADDR((NewSpareAddr>>8)&0xff);
NF_ADDR((NewSectorAddr)&0xff);
NF_ADDR((NewSectorAddr>>8) & 0xff);
if (LB_NEED_EXT_ADDR) {
NF_ADDR((NewSectorAddr >> 16) & 0xff);
}
NF_CMD(CMD_READ3);
// Wait for the Ready bit
NF_DETECT_RB(); // Wait tR(max 12us)
// Read the SectorInfo data (we only need to read first 8 bytes)
pInfo->dwReserved1 = NF_DATA_R4();
rddata = NF_DATA_R4();
// OEM byte
pInfo->bOEMReserved = (BYTE) (rddata & 0xff);
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