reboot.c

三星2440原版bsp

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  File: interrupt.c
//
//  This file implement Samsung S3C2440X SoC specific OALIoCtlxxxx functions.
//
#include <windows.h>
#include <s3c2440x.h>
#include <oal.h>
#include <bsp.h>

extern void CPUPowerWDReset(void);

//------------------------------------------------------------------------------
//
//  Function: OALIoCtlHalReboot
//
//
BOOL OALIoCtlHalReboot(UINT32 code, VOID *pInpBuffer, 
                       UINT32 inpSize, VOID *pOutBuffer, 
                       UINT32 outSize, UINT32 *pOutSize)
{
    //
    // If the board design supports software-controllable hardware reset logic, it should be
    // used.  Because this routine is specific to the S3C2440X CPU, it only uses the watchdog
    // timer to assert reset.  One downside to this approach is that nRSTOUT isn't asserted
    // so any board-level logic isn't reset via this method.  This routine can be overidden in
    // the specific platform code to control board-level reset logic, should it exist.
    //
    volatile S3C2440X_IOPORT_REG *pIOPRegs = (S3C2440X_IOPORT_REG *)OALPAtoVA(S3C2440X_BASE_REG_PA_IOPORT, FALSE);
    volatile S3C2440X_WATCHDOG_REG *pWDRegs = (volatile S3C2440X_WATCHDOG_REG *) 
                                              OALPAtoVA(S3C2440X_BASE_REG_PA_WATCHDOG, FALSE);
    volatile S3C2440X_INTR_REG *pIntrRegs = (volatile S3C2440X_INTR_REG *)
    										  OALPAtoVA(S3C2440X_BASE_REG_PA_INTR, FALSE);	
    BSP_ARGS *pBSPArgs = ((BSP_ARGS *) IMAGE_SHARE_ARGS_UA_START);

    BOOL *pUpdateModeCheck;
    
    pUpdateModeCheck = (BOOL *) OALArgsQuery(OAL_ARGS_QUERY_UPDATEMODE);
    
#ifdef ULDR
    pBSPArgs->fUldrReboot = TRUE ;      
#endif

    RETAILMSG(1, (L"+OALIoCtlHalReboot\r\n"));
    if(*pUpdateModeCheck == TRUE)
    RETAILMSG(1,(TEXT(" UpdateMode = TRUE, May be launching Update Loader !!\r\n")));	
    RETAILMSG(1,(TEXT(" fUldrReboot -> %d, address= %x !!\r\n"),pBSPArgs->fUldrReboot, &pBSPArgs->fUldrReboot)); 
 
	pIntrRegs->INTSUBMSK &= ~(1<<IRQ_SUB_WDT);
	pIntrRegs->INTMSK &= ~(1<<IRQ_WDT_AC97);

    // Setup the watchdog.
    //

	//t_watchdog = 1 / (PCLK / (Prescaler value + 1 ) / Division_factor)
		
	pWDRegs->WTCON = ((S3C2440X_PCLK/1000000-1) << 8) |		/* The prescaler value => 255 + 1	*/
					 (0x00 << 6) |		/* Reserved							*/
					 (0x00 << 5) |		/* Timer enable or disable			*/
					 (0x03 << 3) |		/* The clock division factor => 16	*/
					 (0x00 << 2) |		/* Disable bit of interrupt			*/
					 (0x00 << 1) |		/* Reserved							*/
					 (0x01 << 0);		/* Enable the reset function of timer */
	pWDRegs->WTDAT = 0x1;
	pWDRegs->WTCNT = 0x1;
	
	CPUPowerWDReset();
	    // Should never get to this point...
    //
    OALMSG(OAL_IOCTL&&OAL_FUNC, (L"-OALIoCtlHalReboot\r\n"));

    return(TRUE);

}

//------------------------------------------------------------------------------