📄 startup.s
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OPT 2
INCLUDE kxarm.h
INCLUDE option.inc
INCLUDE s2440addr.inc
INCLUDE memcfg.inc
OPT 1
OPT 128
; Pre-defined constants.
;
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0
DELAY EQU 0x200
; Stack locations.
;
SVCStack EQU (_STACK_BASEADDRESS-0x2800) ; 0x33ff5800 ~
UserStack EQU (_STACK_BASEADDRESS-0x3800) ; 0x33ff4800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400) ; 0x33ff5c00 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000) ; 0x33ff6000 ~
IRQStack EQU (_STACK_BASEADDRESS-0x1000) ; 0x33ff7000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0) ; 0x33ff8000 ~
;---------------------------------------------------------------------------
; 4 LED light function
; The LEDs are located below AMD Flash ROM
MACRO
LED_ON $data
LDR r10, =0x56000054
LDR r11, =$data
MOV r11, r11, lsl #4
STR r11, [r10]
MEND
;---------------------------------------------------------------------------
; for S3C2440 v0.19 board
; 300MHz -> 1.1 +- 0.05 Volt
; 400MHz -> 1.2 +- 0.05 Volt
; 533MHz -> 1.35 +- 0.05 Volt
; /////////////////////////////////////////
; // D4 D3 D2 D1 D0
; // 0 0 1 1 1 // 1.40V/
; // 0 1 0 0 0 // 1.35V/
; // 0 1 0 0 1 // 1.30V
; // 0 1 0 1 0 // 1.25V
; // 0 1 0 1 1 // 1.20V
; // 0 1 1 0 0 // 1.15V
; // 0 1 1 0 1 // 1.10V
; // 0 1 1 1 0 // 1.05V
; // 0 1 1 1 1 // 1.00V
; // 1 0 0 0 1 // 0.95V
; // 1 0 0 1 1 // 0.90V
; // 1 0 1 0 1 // 0.85V
; // 1 0 1 1 1 // 0.80V
GBLA CLKVAL
;CLKVAL SETA 266
;CLKVAL SETA 296
CLKVAL SETA 399
;CLKVAL SETA 315
;CLKVAL SETA 399
;CLKVAL SETA 406
;CLKVAL SETA 530
[ CLKVAL = 406
FCLK EQU (406)
PLLVAL EQU (((64 << 12) + (4 << 4) + 0))
CLKDIVVAL EQU 7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.2 V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 1
D0VAL EQU 1
]
[ CLKVAL = 296
FCLK EQU (296)
PLLVAL EQU (((97 << 12) + (1 << 4) + 2))
CLKDIVVAL EQU 7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.35 V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 0
D0VAL EQU 0
]
[ CLKVAL = 299
FCLK EQU (299)
PLLVAL EQU (((116 << 12) + (5 << 4) + 1))
CLKDIVVAL EQU 7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.35 V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 0
D0VAL EQU 0
]
[ CLKVAL = 266
FCLK EQU (266)
PLLVAL EQU (((118 << 12) + (2 << 4) + 2))
CLKDIVVAL EQU 3 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.05 V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 0
D0VAL EQU 0
]
[ CLKVAL = 315
FCLK EQU (315)
PLLVAL EQU (((85 << 12) + (3 << 4) + 1))
CLKDIVVAL EQU 7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.05 V
D3VAL EQU 1
D2VAL EQU 1
D1VAL EQU 1
D0VAL EQU 0
]
[ CLKVAL = 399
FCLK EQU (399)
PLLVAL EQU (((110 << 12) + (3 << 4) + 1))
CLKDIVVAL EQU 7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.3V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 0
D0VAL EQU 1
]
[ CLKVAL = 530
FCLK EQU (530)
PLLVAL EQU (((86 << 12) + (1 << 4) + 1))
CLKDIVVAL EQU 5 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.35 V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 0
D0VAL EQU 0
]
UPLLVAL EQU (((60 << 12) + (0x4 << 4) + 0x2)) ;48MHz
;---------------------------------------------------------------------------
; Voltage Change function
; The LEDs are located below AMD Flash ROM
MACRO
VOLTAGECHANGE
ldr r8, = GPBDAT ; D4
ldr r9, [r8]
ldr r10, = 0x77f
and r9, r9, r10
ldr r10, = (D4VAL<<7)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPFDAT ; D3~0
ldr r9, [r8]
ldr r10, = 0x0f
and r9, r9, r10
ldr r10, = ((D3VAL<<7)+(D2VAL<<6)+(D1VAL<<5)+(D0VAL<<4))
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBCON ; GPB7: Output
ldr r9, [r8]
ldr r10, = 0x3f3fff
and r9, r9, r10
ldr r10, = (1<<14)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPFCON ; GPF4~7: Output
ldr r9, [r8]
ldr r10, = 0x00ff
and r9, r9, r10
ldr r10, = 0x5500
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBDAT ; Latch enable
ldr r9, [r8]
ldr r10, = ~(0<<8)
and r9, r9, r10
str r9, [r8]
ldr r8, = GPBCON ; GPB8: Output
ldr r9, [r8]
ldr r10, = 0x3cffff
and r9, r9, r10
ldr r10, = (1<<16)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBDAT ; Output enable
ldr r9, [r8]
ldr r10, = (1<<10)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBCON ; GPB10: Output
ldr r9, [r8]
ldr r10, = 0x0fffff
and r9, r9, r10
ldr r10, = (1<<20)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBDAT ; Latch disable
ldr r9, [r8]
ldr r10, = (1<<8)
orr r9, r9, r10
str r9, [r8]
MEND
;---------------------------------------------------------------------------
IMPORT main ; C entrypoint for Steppingstone loader.
EXPORT MMU_EnableICache
EXPORT MMU_SetAsyncBusMode
STARTUPTEXT
LEAF_ENTRY StartUp
b ResetHandler
b .
b .
b .
b .
b .
b .
b .
PowerHandler
str r1, [r0] ; Enable SDRAM self-refresh
str r3, [r2] ; MISCCR Setting
str r5, [r4] ; Power Off !!
b .
LTORG
;-----------------------------------
; Steppingstone loader entry point.
;-----------------------------------
ResetHandler
VOLTAGECHANGE
ldr r0, = GPFCON
ldr r1, = 0x55aa
str r1, [r0]
ldr r0, =WTCON ; disable the watchdog timer.
ldr r1, =0x0
str r1, [r0]
ldr r0, =INTMSK ; mask all first-level interrupts.
ldr r1, =0xffffffff
str r1, [r0]
ldr r0, =INTSUBMSK ; mask all second-level interrupts.
ldr r1, =0x7ff
str r1, [r0]
[ {TRUE}
ldr r0, = CLKDIVN
ldr r1, = CLKDIVVAL
str r1, [r0]
;ands r1, r1, #0xe ; Make AsyncBusMode
;beq %F1
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #R1_nF:OR:R1_iA
mcr p15, 0, r0, c1, c0, 0
1
ldr r0, = LOCKTIME ; To reduce PLL lock time, adjust the LOCKTIME register.
ldr r1, = 0xffffff
str r1, [r0]
ldr r0, = UPLLCON ; Fin=16MHz, Fout=48MHz
ldr r1, = UPLLVAL
str r1, [r0]
nop ; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
nop
nop
nop
nop
nop
nop
ldr r0, = CAMDIVN
ldr r1, = 0
str r1, [r0]
ldr r0, = MPLLCON ; Configure MPLL
ldr r1, = PLLVAL
str r1, [r0]
]
; delay
mov r0, #0x200
5 subs r0, r0, #1
bne %B5
; :::::::::::::::::::::::::::::::::::::::::::::
; BEGIN: Power Management
; - - - - - - - - - - - - - - - - - - - - - - -
ldr r1, =GSTATUS2 ; Determine Booting Mode
ldr r10, [r1]
tst r10, #0x2
beq %F2 ; if not wakeup from PowerOffmode Skip
; MISCCR setting
LED_ON 0xc
str r10, [r1] ; Clear Test
ldr r1, =MISCCR ; MISCCR's Bit 17, 18, 19 -> 0
ldr r0, [r1] ; I don't know why, Just fallow Sample Code.
bic r0, r0, #(3 << 17) ; SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H
str r0, [r1]
; Set memory control registers
add r0, pc, #SMRDATA - (. + 8)
ldr r1, =BWSCON ; BWSCON Address
add r2, r0, #52 ; End address of SMRDATA
loop10
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne loop10
mov r1, #256
loop11
subs r1, r1, #1 ; wait until the SelfRefresh is released.
bne loop11
ldr r2, =0x201000 ; offset into the RAM
add r2, r2, #0x30000000 ; add physical base
mov pc, r2 ; & jump to StartUp address
nop
nop
nop
b .
b %F3 ; if wakeup from PowerOff mode
; goto Power-up code.
; Watchdog reset
2
tst r10, #0x4 ; In case of the wake-up from Watchdog reset,
; go to SDRAM start address(0x3000_0000)
beq %F4 ; If not wakeup from Watchdog reset,
; goto Normal Mode.
mov r0, #4
str r0, [r1] ; Clear the GSTATUS2. Because same code is located in memory address.
; Set memory control registers
10
ldr r0, =SMRDATA
ldr r1, =BWSCON ; BWSCON Address
add r2, r0, #52 ; End address of SMRDATA
loop0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne loop0
mov r1, #256
loop1
subs r1, r1, #1 ; wait until the SelfRefresh is released.
bne loop1
ldr r2, =0x30020048
ldr r9, [r2] ; Check UpdateMode
cmp r9, #1 ; If reboot is called after update package, load IPL.
bne %F5
b %F4
5
ldr r2, =0x30020044 ;Address of updateflag in Arguments
ldr r9, [r2] ; Check UpdateMode
cmp r9, #1 ; If updatemode bit is checked in watchdog-reset, load IPL.
bne %F2
b %F30
2
ldr r2, =0x201000 ; offset into the RAM
add r2, r2, #0x30000000 ; add physical base
mov pc, r2 ; & jump to StartUp address
b .
; Case of Power off reset
3
ldr r1, =MISCCR ; MISCCR's Bit 17, 18, 19 -> 0
ldr r0, [r1] ; I don't know why, Just fallow Sample Code.
bic r0, r0, #(3 << 17) ; SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H
str r0, [r1]
; - - - - - - - - - - - - - - - - - - - - - - -
; END: Power Management
; :::::::::::::::::::::::::::::::::::::::::::::
4
; Configure memory controller
;ldr r0,=SMRDATA
add r0, pc, #SMRDATA - (. + 8)
ldr r1,=BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA
1
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B1
ldr r0,=0x30000000 ; Start address (physical 0x3000.0000).
ldr r10,=0x04000000 ; 64MB of RAM.
20
; Clear RAM.
;
mov r1,#0
mov r2,#0
mov r3,#0
mov r4,#0
mov r5,#0
mov r6,#0
mov r7,#0
mov r8,#0
stmia r0!, {r1-r8}
subs r10, r10, #32
bne %B20
; Initialize stacks.
;
30
mrs r0, cpsr
bic r0, r0, #MODEMASK|NOINT
orr r1, r0, #SVCMODE
msr cpsr_cxsf, r1 ; SVCMode.
ldr sp, =SVCStack
; Jump to main C routine.
;
bl main
LTORG
SMRDATA DATA
; Memory configuration should be optimized for best performance .
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK=75Mhz.
;
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
DCD (0x32|0x80) ; SCLK power saving mode, BANKSIZE 128M/128M, 4-burst.
DCD 0x30 ;MRSR6 CL=3clk
DCD 0x30 ;MRSR7
;DCD 0x20 ; MRSR6 CL=2clk.
;DCD 0x20 ; MRSR7.
;------------------------------------
; MMU Cache/TLB/etc on/off functions
;------------------------------------
R1_I EQU (1<<12)
R1_C EQU (1<<2)
R1_A EQU (1<<1)
R1_M EQU (1)
R1_iA EQU (1<<31)
R1_nF EQU (1<<30)
; void MMU_EnableICache(void);
;
LEAF_ENTRY MMU_EnableICache
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #R1_I
mcr p15, 0, r0, c1, c0, 0
mov pc, lr
; void MMU_SetAsyncBusMode(void);
; FCLK:HCLK= 1:2
;
LEAF_ENTRY MMU_SetAsyncBusMode
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #R1_nF:OR:R1_iA
mcr p15, 0, r0, c1, c0, 0
mov pc, lr
; NAND code...
;
A410_BASE_ADDR EQU 0x2000000
MACRO
LDR4STR1 $src,$tmp1,$tmp2
ldrb $tmp1,[$src]
ldrb $tmp2,[$src]
orr $tmp1,$tmp1,$tmp2,LSL #8
ldrb $tmp2,[$src]
orr $tmp1,$tmp1,$tmp2,LSL #16
ldrb $tmp2,[$src]
orr $tmp1,$tmp1,$tmp2,LSL #24
MEND
EXPORT __RdPage512
__RdPage512
;input:a1(r0)=pPage
stmfd sp!,{r1-r11}
ldr r1,=0x4e000010 ;NFDATA
mov r2,#0x200
10
LDR4STR1 r1,r4,r3
LDR4STR1 r1,r5,r3
LDR4STR1 r1,r6,r3
LDR4STR1 r1,r7,r3
LDR4STR1 r1,r8,r3
LDR4STR1 r1,r9,r3
LDR4STR1 r1,r10,r3
LDR4STR1 r1,r11,r3
stmia r0!,{r4-r11}
subs r2,r2,#32
bne %B10
ldmfd sp!,{r1-r11}
mov pc,lr
END
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