📄 startup.s
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;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
INCLUDE kxarm.h
INCLUDE armmacros.s
INCLUDE s3c2440x.inc
;-------------------------------------------------------------------------------
MemoryMap EQU 0x2a4
BANK_SIZE EQU 0x00100000 ; 1MB per bank in MemoryMap array
BANK_SHIFT EQU 20
; Define RAM space for the Page Tables:
;
PHYBASE EQU 0x30000000 ; physical start
PTs EQU 0x30010000 ; 1st level page table address (PHYBASE + 0x10000)
; save room for interrupt vectors.
;-------------------------------------------------------------------------------
TEXTAREA
IMPORT main
IMPORT OALClearUTLB
IMPORT OALFlushICache
IMPORT OALFlushDCache
; Set up the MMU and Dcache for bootloader.
;
; This routine will initialize the first-level page table based up the contents
; of the MemoryMap array and enable the MMU and caches.
;
; Copy the image to RAM if it's not already running there.
;
; Include Files
; Defines
; for S3C2440A
; 300MHz -> 1.1 +- 0.05 Volt
; 400MHz -> 1.2 +- 0.05 Volt
; 533MHz -> 1.35 +- 0.05 Volt
; /////////////////////////////////////////
; // D4 D3 D2 D1 D0
; // 0 0 1 1 1 // 1.40V/
; // 0 1 0 0 0 // 1.35V/
; // 0 1 0 0 1 // 1.30V
; // 0 1 0 1 0 // 1.25V
; // 0 1 0 1 1 // 1.20V
; // 0 1 1 0 0 // 1.15V
; // 0 1 1 0 1 // 1.10V
; // 0 1 1 1 0 // 1.05V
; // 0 1 1 1 1 // 1.00V
; // 1 0 0 0 1 // 0.95V
; // 1 0 0 1 1 // 0.90V
; // 1 0 1 0 1 // 0.85V
; // 1 0 1 1 1 // 0.80V
D4VAL EQU 0 ; 1.3V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 0
D0VAL EQU 1
;------------------------------------------------------------------------------
; System clock configuration
;PLLVAL EQU (((97 << 12) + (1 << 4) + 2)) ; 296Mhz
PLLVAL EQU (((110 << 12) + (3 << 4) + 1)) ; 399Mhz
CLKDIVVAL EQU 7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
UPLLVAL EQU (((60 << 12) + (0x4 << 4) + 0x2)) ; 48MHz
;UPLLVAL EQU (((60 << 12) + (0x4 << 4) + 0x1)) ; 96MHz
;------------------------------------------------------------------------------
; Data Cache Characteristics.
;
DCACHE_LINES_PER_SET_BITS EQU 6
DCACHE_LINES_PER_SET EQU 64
DCACHE_NUM_SETS EQU 8
DCACHE_SET_INDEX_BIT EQU (32 - DCACHE_LINES_PER_SET_BITS)
DCACHE_LINE_SIZE EQU 32
;------------------------------------------------------------------------------
; Sleep state constants
;
; Location of sleep data
; BUGBUG - this needs to be declared as a local var.
SLEEPDATA_BASE_PHYSICAL EQU 0x30058000
; Sleep State memory locations
SleepState_Data_Start EQU (0)
SleepState_WakeAddr EQU (SleepState_Data_Start + 0)
SleepState_MMUCTL EQU (SleepState_WakeAddr + WORD_SIZE)
SleepState_MMUTTB EQU (SleepState_MMUCTL + WORD_SIZE)
SleepState_MMUDOMAIN EQU (SleepState_MMUTTB + WORD_SIZE)
SleepState_SVC_SP EQU (SleepState_MMUDOMAIN + WORD_SIZE)
SleepState_SVC_SPSR EQU (SleepState_SVC_SP + WORD_SIZE)
SleepState_FIQ_SPSR EQU (SleepState_SVC_SPSR + WORD_SIZE)
SleepState_FIQ_R8 EQU (SleepState_FIQ_SPSR + WORD_SIZE)
SleepState_FIQ_R9 EQU (SleepState_FIQ_R8 + WORD_SIZE)
SleepState_FIQ_R10 EQU (SleepState_FIQ_R9 + WORD_SIZE)
SleepState_FIQ_R11 EQU (SleepState_FIQ_R10 + WORD_SIZE)
SleepState_FIQ_R12 EQU (SleepState_FIQ_R11 + WORD_SIZE)
SleepState_FIQ_SP EQU (SleepState_FIQ_R12 + WORD_SIZE)
SleepState_FIQ_LR EQU (SleepState_FIQ_SP + WORD_SIZE)
SleepState_ABT_SPSR EQU (SleepState_FIQ_LR + WORD_SIZE)
SleepState_ABT_SP EQU (SleepState_ABT_SPSR + WORD_SIZE)
SleepState_ABT_LR EQU (SleepState_ABT_SP + WORD_SIZE)
SleepState_IRQ_SPSR EQU (SleepState_ABT_LR + WORD_SIZE)
SleepState_IRQ_SP EQU (SleepState_IRQ_SPSR + WORD_SIZE)
SleepState_IRQ_LR EQU (SleepState_IRQ_SP + WORD_SIZE)
SleepState_UND_SPSR EQU (SleepState_IRQ_LR + WORD_SIZE)
SleepState_UND_SP EQU (SleepState_UND_SPSR + WORD_SIZE)
SleepState_UND_LR EQU (SleepState_UND_SP + WORD_SIZE)
SleepState_SYS_SP EQU (SleepState_UND_LR + WORD_SIZE)
SleepState_SYS_LR EQU (SleepState_SYS_SP + WORD_SIZE)
SleepState_Data_End EQU (SleepState_SYS_LR + WORD_SIZE)
SLEEPDATA_SIZE EQU (SleepState_Data_End - SleepState_Data_Start) / 4
;---------------------------------------------------------------------------
; 4 LED light function
; The LEDs are located below AMD Flash ROM
MACRO
LED_ON $data
LDR r10, =0x56000054
LDR r11, =$data
MOV r11, r11, lsl #4
STR r11, [r10]
MEND
;---------------------------------------------------------------------------
;---------------------------------------------------------------------------
; Voltage Change function
; The LEDs are located below AMD Flash ROM
MACRO
VOLTAGECHANGE
ldr r8, = GPBDAT ; D4
ldr r9, [r8]
ldr r10, = 0x77f
and r9, r9, r10
ldr r10, = (D4VAL<<7)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPFDAT ; D3~0
ldr r9, [r8]
ldr r10, = 0x0f
and r9, r9, r10
ldr r10, = ((D3VAL<<7)+(D2VAL<<6)+(D1VAL<<5)+(D0VAL<<4))
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBCON ; GPB7: Output
ldr r9, [r8]
ldr r10, = 0x3f3fff
and r9, r9, r10
ldr r10, = (1<<14)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPFCON ; GPF4~7: Output
ldr r9, [r8]
ldr r10, = 0x00ff
and r9, r9, r10
ldr r10, = 0x5500
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBDAT ; Latch enable
ldr r9, [r8]
ldr r10, = ~(0<<8)
and r9, r9, r10
str r9, [r8]
ldr r8, = GPBCON ; GPB8: Output
ldr r9, [r8]
ldr r10, = 0x3cffff
and r9, r9, r10
ldr r10, = (1<<16)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBDAT ; Output enable
ldr r9, [r8]
ldr r10, = (1<<10)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBCON ; GPB10: Output
ldr r9, [r8]
ldr r10, = 0x0fffff
and r9, r9, r10
ldr r10, = (1<<20)
orr r9, r9, r10
str r9, [r8]
ldr r8, = GPBDAT ; Latch disable
ldr r9, [r8]
ldr r10, = (1<<8)
orr r9, r9, r10
str r9, [r8]
MEND
;---------------------------------------------------------------------------
; External Variables
; External Functions
; Global Variables
; Local Variables
; Local Functions
;-------------------------------------------------------------------------------
; Function: Startup
;
; Main entry point for CPU initialization.
;
STARTUPTEXT
LEAF_ENTRY StartUp
; Jump over power-off code.
b ResetHandler
; Power-off the CPU.
str r1, [r0] ; enable SDRAM self-refresh.
str r3, [r2] ; MISCCR setting.
str r5, [r4] ; POWER OFF!!!!!
b .
ResetHandler
VOLTAGECHANGE
; Make sure that TLB & cache are consistent
; mov r0, #0
; mcr p15, 0, r0, c8, c7, 0 ; flush both TLB
; mcr p15, 0, r0, c7, c5, 0 ; invalidate instruction cache
; mcr p15, 0, r0, c7, c6, 0 ; invalidate data cache
ldr r0, = GPFCON
ldr r1, = 0x55aa
str r1, [r0]
ldr r0, = WTCON ; disable watch dog
ldr r1, = 0x0
str r1, [r0]
ldr r0, = INTMSK
ldr r1, = 0xffffffff ; disable all interrupts
str r1, [r0]
ldr r0, = INTSUBMSK
ldr r1, = 0x7ff ; disable all sub interrupt
str r1, [r0]
ldr r0, = INTMOD
mov r1, #0x0 ; set all interrupt as IRQ
str r1, [r0]
[ {FALSE}
bl OALClearUTLB
bl OALFlushICache
ldr r0, = (DCACHE_LINES_PER_SET - 1)
ldr r1, = (DCACHE_NUM_SETS - 1)
ldr r2, = DCACHE_SET_INDEX_BIT
ldr r3, = DCACHE_LINE_SIZE
bl OALFlushDCache
nop
nop
nop
]
[ {TRUE}
ldr r0, = CLKDIVN
ldr r1, = CLKDIVVAL
str r1, [r0]
; ands r1, r1, #0xe ; set AsyncBusMode
; beq %F10
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