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</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>STATUS cacheUnlock
    (
    CACHE_TYPE cache,   /* cache to unlock */
    void *     address, /* virtual address */
    size_t     bytes    /* number of bytes to unlock */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine unlocks all (global) or some (local) entries in the 
specified cache.  Not all caches can perform unlocking.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK, or ERROR if the cache type is invalid or the cache control
is not supported.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./cacheLib.html#top">cacheLib</a></b>

<hr>
<a name="cacheFlush"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>cacheFlush</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>cacheFlush</i>(&nbsp;)</strong> - flush all or some of a specified cache</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>STATUS cacheFlush
    (
    CACHE_TYPE cache,   /* cache to flush */
    void *     address, /* virtual address */
    size_t     bytes    /* number of bytes to flush */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine flushes (writes to memory) all or some of the entries in
the specified cache.  Depending on the cache design, this operation may
also invalidate the cache tags.  For write-through caches, no work needs
to be done since RAM already matches the cached entries.  Note that
write buffers on the chip may need to be flushed to complete the flush.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK, or ERROR if the cache type is invalid or the cache control
is not supported.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./cacheLib.html#top">cacheLib</a></b>

<hr>
<a name="cacheInvalidate"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>cacheInvalidate</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>cacheInvalidate</i>(&nbsp;)</strong> - invalidate all or some of a specified cache</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>STATUS cacheInvalidate
    (
    CACHE_TYPE cache,   /* cache to invalidate */
    void *     address, /* virtual address */
    size_t     bytes    /* number of bytes to invalidate */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine invalidates all or some of the entries in the
specified cache.  Depending on the cache design, the invalidation
may be similar to the flush, or one may invalidate the tags directly.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK, or ERROR if the cache type is invalid or the cache control
is not supported.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./cacheLib.html#top">cacheLib</a></b>

<hr>
<a name="cacheClear"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>cacheClear</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>cacheClear</i>(&nbsp;)</strong> - clear all or some entries from a cache</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>STATUS cacheClear
    (
    CACHE_TYPE cache,   /* cache to clear */
    void *     address, /* virtual address */
    size_t     bytes    /* number of bytes to clear */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine flushes and invalidates all or some entries in the
specified cache.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK, or ERROR if the cache type is invalid or the cache control
is not supported.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./cacheLib.html#top">cacheLib</a></b>

<hr>
<a name="cachePipeFlush"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>cachePipeFlush</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>cachePipeFlush</i>(&nbsp;)</strong> - flush processor write buffers to memory</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>

STATUS cachePipeFlush (void)</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine forces the processor output buffers to write their contents 
to RAM.  A cache flush may have forced its data into the write buffers, 
then the buffers need to be flushed to RAM to maintain coherency.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK, or ERROR if the cache control is not supported.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./cacheLib.html#top">cacheLib</a></b>

<hr>
<a name="cacheTextUpdate"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>cacheTextUpdate</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>cacheTextUpdate</i>(&nbsp;)</strong> - synchronize the instruction and data caches</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>STATUS cacheTextUpdate
    (
    void * address, /* virtual address */
    size_t bytes    /* number of bytes to sync */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine flushes the data cache, then invalidates the instruction 
cache.  This operation forces the instruction cache to fetch code that 
may have been created via the data path.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK, or ERROR if the cache control is not supported.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./cacheLib.html#top">cacheLib</a></b>

<hr>
<a name="cacheDmaMalloc"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>cacheDmaMalloc</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>cacheDmaMalloc</i>(&nbsp;)</strong> - allocate a cache-safe buffer for DMA devices and drivers</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void * cacheDmaMalloc
    (
    size_t bytes /* number of bytes to allocate */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine returns a pointer to a section of memory that will not 
experience any cache coherency problems.  Function pointers in the 
<b>CACHE_FUNCS</b> structure provide access to DMA support routines.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
A pointer to the cache-safe buffer, or NULL.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./cacheLib.html#top">cacheLib</a></b>

<hr>
<a name="cacheDmaFree"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>cacheDmaFree</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>cacheDmaFree</i>(&nbsp;)</strong> - free the buffer acquired with <b><i><a href="./cacheLib.html#cacheDmaMalloc">cacheDmaMalloc</a></i>(&nbsp;)</b></p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>STATUS cacheDmaFree
    (
    void * pBuf /* pointer to malloc/free buffer */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine frees the buffer returned by <b><i><a href="./cacheLib.html#cacheDmaMalloc">cacheDmaMalloc</a></i>(&nbsp;)</b>.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK, or ERROR if the cache control is not supported.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./cacheLib.html#top">cacheLib</a></b>

<hr>
<a name="cacheDrvFlush"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>cacheDrvFlush</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>cacheDrvFlush</i>(&nbsp;)</strong> - flush the data cache for drivers</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>STATUS cacheDrvFlush
    (
    CACHE_FUNCS * pFuncs,  /* pointer to CACHE_FUNCS */
    void *        address, /* virtual address */
    size_t        bytes    /* number of bytes to flush */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine flushes the data cache entries using the function pointer 
from the specified set.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK, or ERROR if the cache control is not supported.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./cacheLib.html#top">cacheLib</a></b>

<hr>
<a name="cacheDrvInvalidate"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>cacheDrvInvalidate</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>cacheDrvInvalidate</i>(&nbsp;)</strong> - invalidate data cache for drivers</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>STATUS cacheDrvInvalidate
    (
    CACHE_FUNCS * pFuncs,  /* pointer to CACHE_FUNCS */
    void *        address, /* virtual address */
    size_t        bytes    /* no. of bytes to invalidate */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine invalidates the data cache entries using the function pointer 
from the specified set.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK, or ERROR if the cache control is not supported.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./cacheLib.html#top">cacheLib</a></b>

<hr>
<a name="cacheDrvVirtToPhys"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>cacheDrvVirtToPhys</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>cacheDrvVirtToPhys</i>(&nbsp;)</strong> - translate a virtual address for drivers</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void * cacheDrvVirtToPhys
    (
    CACHE_FUNCS * pFuncs, /* pointer to CACHE_FUNCS */
    void *        address /* virtual address */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine performs a virtual-to-physical address translation using the 
function pointer from the specified set.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
The physical address translation of a virtual address argument.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./cacheLib.html#top">cacheLib</a></b>

<hr>
<a name="cacheDrvPhysToVirt"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>cacheDrvPhysToVirt</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>cacheDrvPhysToVirt</i>(&nbsp;)</strong> - translate a physical address for drivers</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void * cacheDrvPhysToVirt
    (
    CACHE_FUNCS * pFuncs, /* pointer to CACHE_FUNCS */
    void *        address /* physical address */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine performs a physical-to-virtual address translation using the 
function pointer from the specified set.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
The virtual address that maps to the physical address argument.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./cacheLib.html#top">cacheLib</a></b>

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