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<html><head><!-- /vobs/wpwr/docs/vxworks/ref/cacheArchLib.html - generated by refgen from cacheArchLib.c --> <title> cacheArchLib </title></head><body bgcolor="#FFFFFF"> <hr><a name="top"></a><p align=right><a href="libIndex.html"><i>VxWorks Reference Manual : Libraries</i></a></p></blockquote><h1>cacheArchLib</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>cacheArchLib</strong> - architecture-specific cache management library </p></blockquote><h4>ROUTINES</h4><blockquote><p><p><b><i><a href="./cacheArchLib.html#cacheArchLibInit">cacheArchLibInit</a></i>( )</b> - initialize the cache library<br><b><i><a href="./cacheArchLib.html#cacheArchClearEntry">cacheArchClearEntry</a></i>( )</b> - clear an entry from a cache (68K, x86)<br><b><i><a href="./cacheArchLib.html#cacheStoreBufEnable">cacheStoreBufEnable</a></i>( )</b> - enable the store buffer (MC68060 only)<br><b><i><a href="./cacheArchLib.html#cacheStoreBufDisable">cacheStoreBufDisable</a></i>( )</b> - disable the store buffer (MC68060 only)<br><p></blockquote><h4>DESCRIPTION</h4><blockquote><p>This library contains architecture-specific cache library functions forthe following processor cache families: Motorola 68K, Intel 960, Intel x86, PowerPC,ARM, and the Solaris, HP-UX, and NT simulators. Each routine description indicateswhich architecture families support it. Within families, different members supportdifferent cache mechanisms; thus, some operations cannot be performed by certain processors because they lack particular functionalities. In such cases, the routinesin this library return ERROR. Processor-specific constraints are addressed in themanual entries for routines in this library. If the caches are unavailable or uncontrollable, the routines return ERROR. The exception to this rule is the 68020;although the 68020 has no cache, data cache operations return OK.<p>The SPARC and MIPS archetecture families have cache-related routines in individual BSPlibraries. See the reference pages for the individual libraries and routines.<p></blockquote><h4>INCLUDE FILES</h4><blockquote><p><b>cacheLib.h</b>, <b>mmuLib.h</b> (ARM only)<p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheArchLib.html#top">cacheArchLib</a></b>, <b><a href="./cacheLib.html#top">cacheLib</a></b>, <b><a href="./vmLib.html#top">vmLib</a></b><hr><a name="cacheArchLibInit"></a><p align=right><a href="rtnIndex.html"><i>Libraries : Routines</i></a></p></blockquote><h1><i>cacheArchLibInit</i>( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong><i>cacheArchLibInit</i>( )</strong> - initialize the cache library</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>STATUS cacheArchLibInit ( CACHE_MODE instMode, /* instruction cache mode */ CACHE_MODE dataMode /* data cache mode */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine initializes the cache library for the following processor cache families: Motorola 68K, Intel 960, Intel x86, PowerPC ARM, and the Solaris, HP-UX, and NT simulators. It initializes the function pointers and configures thecaches to the specified cache modes.<p></blockquote><h4>68K PROCESSORS</h4><blockquote><p>The caching modes vary for members of the 68K processor family:<p><table><tr valign=top><td align=left></blockquote><h4>68020</h4><blockquote><p></td><td align=left> <b>CACHE_WRITETHROUGH</b> </td><td align=left> (instruction cache only)</tr><tr valign=top><td align=left></tr><tr valign=top><td align=left></blockquote><h4>68030</h4><blockquote><p></td><td align=left> <b>CACHE_WRITETHROUGH</b> </td><td align=left></tr><tr valign=top><td align=left> </td><td align=left> <b>CACHE_BURST_ENABLE</b> </td><td align=left></tr><tr valign=top><td align=left> </td><td align=left> <b>CACHE_BURST_DISABLE</b> </td><td align=left></tr><tr valign=top><td align=left> </td><td align=left> <b>CACHE_WRITEALLOCATE</b> </td><td align=left> (data cache only)</tr><tr valign=top><td align=left> </td><td align=left> <b>CACHE_NO_WRITEALLOCATE</b> </td><td align=left> (data cache only)</tr><tr valign=top><td align=left></tr><tr valign=top><td align=left></blockquote><h4>68040</h4><blockquote><p></td><td align=left> <b>CACHE_WRITETHROUGH</b> </td><td align=left></tr><tr valign=top><td align=left> </td><td align=left> <b>CACHE_COPYBACK</b> </td><td align=left> (data cache only)</tr><tr valign=top><td align=left> </td><td align=left> <b>CACHE_INH_SERIAL</b> </td><td align=left> (data cache only)</tr><tr valign=top><td align=left> </td><td align=left> <b>CACHE_INH_NONSERIAL</b> </td><td align=left> (data cache only)</tr><tr valign=top><td align=left> </td><td align=left> <b>CACHE_BURST_ENABLE</b> </td><td align=left> (data cache only)</tr><tr valign=top><td align=left> </td><td align=left> <b>CACHE_NO_WRITEALLOCATE</b> </td><td align=left> (data cache only)</tr><tr valign=top><td align=left></tr><tr valign=top><td align=left></blockquote><h4>68060</h4><blockquote><p></td><td align=left> <b>CACHE_WRITETHROUGH</b> </td><td align=left></tr><tr valign=top><td align=left> </td><td align=left> <b>CACHE_COPYBACK</b> </td><td align=left> (data cache only)</tr><tr valign=top><td align=left> </td><td align=left> <b>CACHE_INH_PRECISE</b> </td><td align=left> (data cache only)</tr><tr valign=top><td align=left> </td><td align=left> <b>CACHE_INH_IMPRECISE</b> </td><td align=left> (data cache only)</tr><tr valign=top><td align=left> </td><td align=left> <b>CACHE_BURST_ENABLE</b> </td><td align=left> (data cache only)</tr><tr valign=top><td align=left></tr></tr></table>The write-through, copy-back, serial, non-serial, precise and non precisemodes change the state of the data transparent translation register (DTTR0)CM bits. Only DTTR0 is modified, since it typically maps DRAM space.<p></blockquote><h4>X86 PROCESSORS</h4><blockquote><p>The caching mode <b>CACHE_WRITETHROUGH</b> is available for the x86 processor family.<p></blockquote><h4>POWER PC PROCESSORS</h4><blockquote><p>Modes should be set before caching is enabled. If two contradictory flags are set (for example, enable/disable), no action is taken for any of the input flags.<p></blockquote><h4>ARM PROCESSORS</h4><blockquote><p>The caching capabilities and modes vary for members of the ARM processorfamily. All caches are provided on-chip, so cache support is mostly anarchitecture issue, not a BSP issue. However, the memory map isBSP-specific and some functions need knowledge of the memory map, so theyhave to be provided in the BSP.<dl><dt>ARM7TDMI (In ARM or Thumb state)<dd>No cache or MMU at all. Dummy routine provided, so that<b>INCLUDE_CACHE_SUPPORT</b> can be defined (the default BSP configuration).<p><dt>ARM710A<dd>Combined instruction and data cache. Actually a write-through cache, butseparate write-buffer effectively makes this a copy-back cache if thewrite-buffer is enabled. Use write-through/copy-back argument to decidewhether to enable write buffer. Data and instruction cache modes must beidentical.<p><dt>ARM810<dd>Combined instruction and data cache. Write-through and copy-back cachemodes, but separate write-buffer effectively makes even write-through acopy-back cache as all writes are buffered, when cache is enabled. Dataand instruction cache modes must be identical.<p><dt>ARMSA110<dd> Separate instruction and data caches. Write-through and copy-back cachemode for data, but separate write-buffer effectively makes evenwrite-through a copy-back cache as all writes are buffered, when cacheis enabled. </dl><p></blockquote><h4>RETURNS</h4><blockquote><p>OK</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheArchLib.html#top">cacheArchLib</a></b><hr><a name="cacheArchClearEntry"></a><p align=right><a href="rtnIndex.html"><i>Libraries : Routines</i></a></p></blockquote><h1><i>cacheArchClearEntry</i>( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong><i>cacheArchClearEntry</i>( )</strong> - clear an entry from a cache (68K, x86)</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>STATUS cacheArchClearEntry ( CACHE_TYPE cache, /* cache to clear entry for */ void * address /* entry to clear */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine clears a specified entry from the specified cache.<p>For 68040 processors, this routine clears the cache line from the cachein which the cache entry resides.<p>For the MC68060 processor, when the instruction cache is cleared (invalidated)the branch cache is also invalidated by the hardware. One line in the branchcache cannot be invalidated so each time the branch cache is entirelyinvalidated.<p>For 386 processors and PENTIUMPRO processors with <b>SNOOP_ENABLED</b> data cache mode,this routine does nothing.<p></blockquote><h4>RETURNS</h4><blockquote><p>OK, or ERROR if the cache type is invalid or the cache controlis not supported.</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheArchLib.html#top">cacheArchLib</a></b><hr><a name="cacheStoreBufEnable"></a><p align=right><a href="rtnIndex.html"><i>Libraries : Routines</i></a></p></blockquote><h1><i>cacheStoreBufEnable</i>( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong><i>cacheStoreBufEnable</i>( )</strong> - enable the store buffer (MC68060 only)</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void cacheStoreBufEnable (void)</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine sets the ESB bit of the Cache Control Register (CACR) toenable the store buffer. To maximize performance, the four-entryfirst-in-first-out (FIFO) store buffer is used to defer pending writesto writethrough or cache-inhibited imprecise pages.<p></blockquote><h4>RETURNS</h4><blockquote><p>N/A</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheArchLib.html#top">cacheArchLib</a></b><hr><a name="cacheStoreBufDisable"></a><p align=right><a href="rtnIndex.html"><i>Libraries : Routines</i></a></p></blockquote><h1><i>cacheStoreBufDisable</i>( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong><i>cacheStoreBufDisable</i>( )</strong> - disable the store buffer (MC68060 only)</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void cacheStoreBufDisable (void)</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine resets the ESB bit of the Cache Control Register (CACR) todisable the store buffer.<p></blockquote><h4>RETURNS</h4><blockquote><p>N/A</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheArchLib.html#top">cacheArchLib</a></b></body></html>⌨️ 快捷键说明
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