📄 el3c90xend.html
字号:
<html><head><!-- /vobs/wpwr/docs/vxworks/ref/el3c90xEnd.html - generated by refgen from el3c90xEnd.c --> <title> el3c90xEnd </title></head><body bgcolor="#FFFFFF"> <hr><a name="top"></a><p align=right><a href="libIndex.html"><i>VxWorks Reference Manual : Libraries</i></a></p></blockquote><h1>el3c90xEnd</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>el3c90xEnd</strong> - END network interface driver for 3COM 3C90xB XL </p></blockquote><h4>ROUTINES</h4><blockquote><p><p><b><i><a href="./el3c90xEnd.html#el3c90xEndLoad">el3c90xEndLoad</a></i>( )</b> - initialize the driver and device<br><b><i><a href="./el3c90xEnd.html#el3c90xInitParse">el3c90xInitParse</a></i>( )</b> - parse the initialization string<br><p></blockquote><h4>DESCRIPTION </h4><blockquote><p>This module implements the device driver for the 3COM EtherLink Xl andFast EtherLink XL PCI network interface cards.<p>The 3c90x PCI ethernet controller is inherently little endian becausethe chip is designed to operate on a PCI bus which is a little endianbus. The software interface to the driver is divided into three parts.The first part is the PCI configuration registers and their set up. This part is done at the BSP level in the various BSPs which use thisdriver. The second and third part are dealt in the driver. The secondpart of the interface comprises of the I/O control registers and theirprogramming. The third part of the interface comprises of the descriptorsand the buffers. <p>This driver is designed to be moderately generic, operating unmodifiedacross the range of architectures and targets supported by VxWorks. Toachieve this, the driver must be given several target-specific parameters,and some external support routines must be provided. These target-specificvalues and the external support routines are described below.<p>This driver supports multiple units per CPU. The driver can beconfigured to support big-endian or little-endian architectures. Itcontains error recovery code to handle known device errata related to DMAactivity. <p>Big endian processors can be connected to the PCI bus through some controllerswhich take care of hardware byte swapping. In such cases all the registers which the chip DMA s to have to be swapped and written to, so that when thehardware swaps the accesses, the chip would see them correctly. The chip stillhas to be programmed to operated in little endian mode as it is on the PCI bus.If the cpu board hardware automatically swaps all the accesses to and from thePCI bus, then input and output byte stream need not be swapped.<p>The 3c90x series chips use a bus-master DMA interface for transferingpackets to and from the controller chip. Some of the old 3c59x cardsalso supported a bus master mode, however for those chipsyou could only DMA packets to and from a contiguous memory buffer. Fortransmission this would mean copying the contents of the queued <b>M_BLK</b>chain into a an <b>M_BLK</b> cluster and then DMAing the cluster. This extracopy would sort of defeat the purpose of the bus master support forany packet that doesn't fit into a single <b>M_BLK</b>. By contrast, the 3c90x cardssupport a fragment-based bus master mode where <b>M_BLK</b> chains can beencapsulated using TX descriptors. This is also called the gather technique,where the fragments in an mBlk chain are directly incorporated into thedownload transmit descriptor. This avoids any copying of data from themBlk chain. <p></blockquote><h4>NETWORK CARDS SUPPORTED</h4><blockquote><p><p><br> - 3Com 3c900-TPO 10Mbps/RJ-45<br> - 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC<br> - 3Com 3c905-TX 10/100Mbps/RJ-45<br> - 3Com 3c905-T4 10/100Mbps/RJ-45<br> - 3Com 3c900B-TPO 10Mbps/RJ-45<br> - 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC<br> - 3Com 3c905B-TX 10/100Mbps/RJ-45<br> - 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic<br> - 3Com 3c980-TX 10/100Mbps server adapter<br> - Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45<p></blockquote><h4>BOARD LAYOUT</h4><blockquote><p>This device is on-board. No jumpering diagram is necessary.<p></blockquote><h4>EXTERNAL INTERFACE</h4><blockquote><p>The only external interface is the <b><i><a href="./el3c90xEnd.html#el3c90xEndLoad">el3c90xEndLoad</a></i>( )</b> routine, which expectsthe <i>initString</i> parameter as input. This parameter passes in a colon-delimited string of the format:<p><i>unit</i>:<i>devMemAddr</i>:<i>devIoAddr</i>:<i>pciMemBase:<vecNum</i>:<i>intLvl</i>:<i>memAdrs</i>:<i>memSize</i>:<i>memWidth</i>:<i>flags</i>:<i>buffMultiplier</i><p>The <b><i><a href="./el3c90xEnd.html#el3c90xEndLoad">el3c90xEndLoad</a></i>( )</b> function uses <b><i><a href="./ansiString.html#strtok">strtok</a></i>( )</b> to parse the string.<p></blockquote><h4>TARGET-SPECIFIC PARAMETERS</h4><blockquote><p><dl><dt><i>unit</i><dd>A convenient holdover from the former model. This parameter is used onlyin the string name for the driver.<p><dt><i>devMemAddr</i><dd>This parameter in the memory base address of the device registers in thememory map of the CPU. It indicates to the driver where to find theregister set. < This parameter should be equal to NONE if the devicedoes not support memory mapped registers.<p><p><dt><i>devIoAddr</i><dd>This parameter in the IO base address of the device registers in theIO map of some CPUs. It indicates to the driver where to find the RDPregister. If both <i>devIoAddr</i> and <i>devMemAddr</i> are given then the devicechooses <i>devMemAddr</i> which is a memory mapped register base address.This parameter should be equal to NONE if the device does not support IO mapped registers.<p>. <i>pciMemBase</i>This parameter is the base address of the CPU memory as seen from thePCI bus. This parameter is zero for most intel architectures.<p><dt><i>vecNum</i><dd>This parameter is the vector associated with the device interrupt.This driver configures the LANCE device to generate hardware interruptsfor various events within the device; thus it containsan interrupt handler routine. The driver calls <b><i><a href="./intArchLib.html#intConnect">intConnect</a></i>( )</b> to connect its interrupt handler to the interrupt vector generated as a result of the LANCE interrupt.<p><dt><i>intLvl</i><dd>Some targets use additional interrupt controller devices to help organizeand service the various interrupt sources. This driver avoids allboard-specific knowledge of such devices. During the driver'sinitialization, the external routine <b><i>sysEl3c90xIntEnable</i>( )</b> is called toperform any board-specific operations required to allow the servicing of aNIC interrupt. For a description of <b><i>sysEl3c90xIntEnable</i>( )</b>, see "ExternalSupport Requirements" below.<p><dt><i>memAdrs</i><dd>This parameter gives the driver the memory address to carve out itsbuffers and data structures. If this parameter is specified to beNONE then the driver allocates cache coherent memory for buffersand descriptors from the system pool.The 3C90x NIC is a DMA type of device and typically shares access tosome region of memory with the CPU. This driver is designed for systemsthat directly share memory between the CPU and the NIC. Itassumes that this shared memory is directly available to itwithout any arbitration or timing concerns.<p><dt><i>memSize</i><dd>This parameter can be used to explicitly limit the amount of sharedmemory (bytes) this driver will use. The constant NONE can be used toindicate no specific size limitation. This parameter is used only ifa specific memory region is provided to the driver.<p><dt><i>memWidth</i><dd>Some target hardware that restricts the shared memory region to aspecific location also restricts the access width to this region bythe CPU. On these targets, performing an access of an invalid widthwill cause a bus error.<p>This parameter can be used to specify the number of bytes of accesswidth to be used by the driver during access to the shared memory.The constant NONE can be used to indicate no restrictions.<p>Current internal support for this mechanism is not robust; implementation may not work on all targets requiring these restrictions.<p><dt><i>flags</i><dd>This is parameter is used for future use, currently its value should bezero.<p><dt><i>buffMultiplier</i><dd>This parameter is used increase the number of buffers allocated in thedriver pool. If this parameter is -1 then a default multiplier of 2 ischoosen. With a multiplier of 2 the total number of clusters allocatedis 64 which is twice the cumulative number of upload and download descriptors.The device has 16 upload and 16 download descriptors. For example on choosingthe buffer multiplier of 3, the total number of clusters allocated will be96 ((16 + 16)*3). There are as many clBlks as the number of clusters.The number of mBlks allocated are twice the number of clBlks.By default there are 64 clusters, 64 clBlks and 128 mBlks allocated in thepool for the device. Depending on the load of the system increase thenumber of clusters allocated by incrementing the buffer multiplier.<p></dl>⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -