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<html><head><!-- /vobs/wpwr/docs/vxworks/ref/cacheI960CxALib.html - generated by refgen from ../i960/cacheI960CxALib.s --> <title> cacheI960CxALib </title></head><body bgcolor="#FFFFFF"> <hr><a name="top"></a><p align=right><a href="libIndex.html"><i>VxWorks Reference Manual : Libraries</i></a></p></blockquote><h1>cacheI960CxALib</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>cacheI960CxALib</strong> - I960Cx cache management assembly routines </p></blockquote><h4>ROUTINES</h4><blockquote><p><p><b><i><a href="./cacheI960CxALib.html#cacheI960CxICDisable">cacheI960CxICDisable</a></i>( )</b> - disable the I960Cx instruction cache (i960)<br><b><i><a href="./cacheI960CxALib.html#cacheI960CxICEnable">cacheI960CxICEnable</a></i>( )</b> - enable the I960Cx instruction cache (i960)<br><b><i><a href="./cacheI960CxALib.html#cacheI960CxICInvalidate">cacheI960CxICInvalidate</a></i>( )</b> - invalidate the I960Cx instruction cache (i960)<br><b><i><a href="./cacheI960CxALib.html#cacheI960CxICLoadNLock">cacheI960CxICLoadNLock</a></i>( )</b> - load and lock I960Cx 512-byte instruction cache (i960)<br><b><i><a href="./cacheI960CxALib.html#cacheI960CxIC1kLoadNLock">cacheI960CxIC1kLoadNLock</a></i>( )</b> - load and lock I960Cx 1KB instruction cache (i960)<br><p></blockquote><h4>DESCRIPTION</h4><blockquote><p>This library contains Intel I960Cx cache management routines written inassembly language. The I960CX utilize a 1KB instruction cache andno data cache.<p>For general information about caching, see the manual entry for cacheLib.<p></blockquote><h4>INCLUDE FILES</h4><blockquote><p><b>cacheLib.h</b><p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheI960CxALib.html#top">cacheI960CxALib</a></b>, <b><a href="./cacheI960CxLib.html#top">cacheI960CxLib</a></b>, <b><a href="./cacheLib.html#top">cacheLib</a></b>, <i>I960Cx Processors User's Manual </i><hr><a name="cacheI960CxICDisable"></a><p align=right><a href="rtnIndex.html"><i>Libraries : Routines</i></a></p></blockquote><h1><i>cacheI960CxICDisable</i>( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong><i>cacheI960CxICDisable</i>( )</strong> - disable the I960Cx instruction cache (i960)</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void cacheI960CxICDisable (void)</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine disables the I960Cx instruction cache.<p></blockquote><h4>RETURNS</h4><blockquote><p>N/A</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheI960CxALib.html#top">cacheI960CxALib</a></b><hr><a name="cacheI960CxICEnable"></a><p align=right><a href="rtnIndex.html"><i>Libraries : Routines</i></a></p></blockquote><h1><i>cacheI960CxICEnable</i>( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong><i>cacheI960CxICEnable</i>( )</strong> - enable the I960Cx instruction cache (i960)</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void cacheI960CxICEnable ( void )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine enables the I960Cx instruction cache.<p></blockquote><h4>RETURNS</h4><blockquote><p>N/A</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheI960CxALib.html#top">cacheI960CxALib</a></b><hr><a name="cacheI960CxICInvalidate"></a><p align=right><a href="rtnIndex.html"><i>Libraries : Routines</i></a></p></blockquote><h1><i>cacheI960CxICInvalidate</i>( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong><i>cacheI960CxICInvalidate</i>( )</strong> - invalidate the I960Cx instruction cache (i960)</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void cacheI960CxICInvalidate ( void )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p><p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheI960CxALib.html#top">cacheI960CxALib</a></b><hr><a name="cacheI960CxICLoadNLock"></a><p align=right><a href="rtnIndex.html"><i>Libraries : Routines</i></a></p></blockquote><h1><i>cacheI960CxICLoadNLock</i>( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong><i>cacheI960CxICLoadNLock</i>( )</strong> - load and lock I960Cx 512-byte instruction cache (i960)</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void cacheI960CxICLoadNLock ( void * address )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine loads and locks the I960Cx 512-byte instruction cache.The loaded address must be an address of a quad-word aligned block of memory.The instructions loaded into the cache can only be accessed by selected interrupts which vector to the addresses of these instructions. Theload-and-lock mechanism selectively optimizes latency and throughput forinterrupts.<p></blockquote><h4>RETURNS</h4><blockquote><p>N/A</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheI960CxALib.html#top">cacheI960CxALib</a></b><hr><a name="cacheI960CxIC1kLoadNLock"></a><p align=right><a href="rtnIndex.html"><i>Libraries : Routines</i></a></p></blockquote><h1><i>cacheI960CxIC1kLoadNLock</i>( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong><i>cacheI960CxIC1kLoadNLock</i>( )</strong> - load and lock I960Cx 1KB instruction cache (i960)</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void cacheI960CxIC1kLoadNLock ( void * address )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine loads and locks the I960Cx 1KB instruction cache.The loaded address must be an address of a quad-word aligned block of memory.The instructions loaded into the cache can only be accessed by selectedinterrupts which vector to the addresses of these instructions. Theload-and-lock mechanism selectively optimizes latency and throughput forinterrupts.<p></blockquote><h4>RETURNS</h4><blockquote><p>N/A</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheI960CxALib.html#top">cacheI960CxALib</a></b></body></html>⌨️ 快捷键说明
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