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<html><head><!-- /vobs/wpwr/docs/vxworks/ref/ln97xEnd.html - generated by refgen from ln97xEnd.c --> <title> ln97xEnd </title></head><body bgcolor="#FFFFFF"> <hr><a name="top"></a><p align=right><a href="libIndex.html"><i>VxWorks Reference Manual :  Libraries</i></a></p></blockquote><h1>ln97xEnd</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  <p><strong>ln97xEnd</strong> - END style AMD Am79C97X PCnet-PCI Ethernet driver </p></blockquote><h4>ROUTINES</h4><blockquote><p><p><b><i><a href="./ln97xEnd.html#ln97xEndLoad">ln97xEndLoad</a></i>(&nbsp;)</b>  -  initialize the driver and device<br><b><i><a href="./ln97xEnd.html#ln97xInitParse">ln97xInitParse</a></i>(&nbsp;)</b>  -  parse the initialization string<br><p></blockquote><h4>DESCRIPTION  </h4><blockquote><p>This module implements the Advanced Micro Devices Am79C971Am79C972 and Am79C973 PCnet-PCI Ethernet 32 bit network interface driver.<p>The PCnet-PCI ethernet controller is inherently little endian becausethe chip is designed to operate on a PCI bus which is a little endianbus. The software interface to the driver is divided into three parts.The first part is the PCI configuration registers and their set up. This part is done at the BSP level in the various BSPs which use thisdriver. The second and third part are dealt in the driver. The secondpart of the interface comprises of the I/O control registers and theirprogramming. The third part of the interface comprises of the descriptorsand the buffers. <p>This driver is designed to be moderately generic, operating unmodifiedacross the range of architectures and targets supported by VxWorks.  Toachieve this, the driver must be given several target-specific parameters,and some external support routines must be provided. These target-specificvalues and the external support routines are described below.<p>This driver supports multiple units per CPU.  The driver can beconfigured to support big-endian or little-endian architectures.  Itcontains error recovery code to handle known device errata related to DMAactivity. <p>Big endian processors can be connected to the PCI bus through some controllerswhich take care of hardware byte swapping. In such cases all the registers which the chip DMA s to have to be swapped and written to, so that when thehardware swaps the accesses, the chip would see them correctly. The chip stillhas to be programmed to operated in little endian mode as it is on the PCI bus.If the cpu board hardware automatically swaps all the accesses to and from thePCI bus, then input and output byte stream need not be swapped. <p></blockquote><h4>BOARD LAYOUT</h4><blockquote><p>This device is on-board.  No jumpering diagram is necessary.<p></blockquote><h4>EXTERNAL INTERFACE</h4><blockquote><p>The only external interface is the <b><i><a href="./ln97xEnd.html#ln97xEndLoad">ln97xEndLoad</a></i>(&nbsp;)</b> routine, which expectsthe <i>initString</i> parameter as input.  This parameter passes in a colon-delimited string of the format:<p><i>unit</i>:<i>devMemAddr</i>:<i>devIoAddr</i>:<i>pciMemBase:<vecNum</i>:<i>intLvl</i>:<i>memAdrs</i>:<i>memSize</i>:<i>memWidth</i>:<i>csr3b</i>:<i>offset</i>:<i>flags</i><p>The <b><i><a href="./ln97xEnd.html#ln97xEndLoad">ln97xEndLoad</a></i>(&nbsp;)</b> function uses <b><i><a href="./ansiString.html#strtok">strtok</a></i>(&nbsp;)</b> to parse the string.<p></blockquote><h4>TARGET-SPECIFIC PARAMETERS</h4><blockquote><p><dl><dt><i>unit</i><dd>A convenient holdover from the former model.  This parameter is used onlyin the string name for the driver.<p><dt><i>devMemAddr</i><dd>This parameter in the memory base address of the device registers in thememory map of the CPU. It indicates to the driver where to find theRDP register.The LANCE presents two registers to the external interface, the RDP (registerdata port) and RAP (register address port) registers.  This driver assumes that these two registers occupy two unique addresses in a memory spacethat is directly accessible by the CPU executing this driver.  The driverassumes that the RDP register is mapped at a lower address than the RAPregister; the RDP register is therefore derived from the "base address."This parameter should be equal to NONE if memory map is not used.<p><dt><i>devIoAddr</i><dd>This parameter in the IO base address of the device registers in theIO map of some CPUs. It indicates to the driver where to find the RDPregister. If both <i>devIoAddr</i> and <i>devMemAddr</i> are given then the devicechooses <i>devMemAddr</i> which is a memory mapped register base address.This parameter should be equal to NONE if IO map is not used.<p><dt><i>pciMemBase</i><dd>This parameter is the base address of the CPU memory as seen from thePCI bus. This parameter is zero for most intel architectures.<p><dt><i>vecNum</i><dd>This parameter is the vector associated with the device interrupt.This driver configures the LANCE device to generate hardware interruptsfor various events within the device; thus it containsan interrupt handler routine.  The driver calls <b><i><a href="./intArchLib.html#intConnect">intConnect</a></i>(&nbsp;)</b> to connect its interrupt handler to the interrupt vector generated as a result of the LANCE interrupt.<p><dt><i>intLvl</i><dd>Some targets use additional interrupt controller devices to help organizeand service the various interrupt sources.  This driver avoids allboard-specific knowledge of such devices.  During the driver'sinitialization, the external routine <b><i>sysLan97xIntEnable</i>(&nbsp;)</b> is called toperform any board-specific operations required to allow the servicing of aLANCE interrupt.  For a description of <b><i>sysLan97xIntEnable</i>(&nbsp;)</b>, see "ExternalSupport Requirements" below.<p><dt><i>memAdrs</i><dd>This parameter gives the driver the memory address to carve out itsbuffers and data structures. If this parameter is specified to beNONE then the driver allocates cache coherent memory for buffersand descriptors from the system pool.The LANCE device is a DMA type of device and typically shares access tosome region of memory with the CPU.  This driver is designed for systemsthat directly share memory between the CPU and the LANCE.  Itassumes that this shared memory is directly available to itwithout any arbitration or timing concerns.<p><dt><i>memSize</i><dd>This parameter can be used to explicitly limit the amount of sharedmemory (bytes) this driver will use.  The constant NONE can be used toindicate no specific size limitation.  This parameter is used only ifa specific memory region is provided to the driver.<p><dt><i>memWidth</i><dd>Some target hardware that restricts the shared memory region to aspecific location also restricts the access width to this region bythe CPU.  On these targets, performing an access of an invalid widthwill cause a bus error.<p>This parameter can be used to specify the number of bytes of accesswidth to be used by the driver during access to the shared memory.The constant NONE can be used to indicate no restrictions.<p>Current internal support for this mechanism is not robust; implementation may not work on all targets requiring these restrictions.<p><dt><i>csr3b</i><dd>The LANCE control register #3 determines the bus mode of the device,allowing the support of big-endian and little-endian architectures.This parameter, defined as "UINT32 lnCSR_3B", is the value that willbe placed into LANCE control register #3.  The default value supportsMotorola-type buses.  For information about changing this parameter, see the manual. Normally for devices on the PCI bus this should always belittle endian. This value is zero normally<p><dt><i>offset</i><dd>This parameter specifies the offset from which the packet has to beloaded from the begining of the device buffer. Normally this parameter iszero except for architectures which access long words only on alignedaddresses. For these architectures the value of this offset should be 2.<p><dt><i>flags</i><dd>This is parameter is used for future use, currently its value should bezero.<p></dl></blockquote><h4>EXTERNAL SUPPORT REQUIREMENTS</h4><blockquote><p><p>This driver requires several external support functions, defined as macros:<pre>    SYS_INT_CONNECT(pDrvCtrl, routine, arg)

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