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<html><head><!-- /vobs/wpwr/docs/vxworks/ref/motFecEnd.html - generated by refgen from motFecEnd.c --> <title> motFecEnd </title></head><body bgcolor="#FFFFFF"> <hr><a name="top"></a><p align=right><a href="libIndex.html"><i>VxWorks Reference Manual : Libraries</i></a></p></blockquote><h1>motFecEnd</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>motFecEnd</strong> - END style Motorola FEC Ethernet network interface driver </p></blockquote><h4>ROUTINES</h4><blockquote><p><p><b><i><a href="./motFecEnd.html#motFecEndLoad">motFecEndLoad</a></i>( )</b> - initialize the driver and device<br><p></blockquote><h4>DESCRIPTION</h4><blockquote><p>This module implements a Motorola Fast Ethernet Controller (FEC) network interface driver. The FEC is fully compliant with the IEEE 802.3 10Base-T and 100Base-T specifications. Hardware support ofthe Media Independent Interface (MII) is built-in in the chip.<p>The FEC establishes a shared memory communication system with the CPU,which is divided into two parts: the Control/Status Registers (CSR),and the buffer descriptors (BD). <p>The CSRs reside in the MPC860T Communication Controller's internal RAM.They are used for mode control and to extract status information of a global nature. For instance, the types of events that should generate an interrupt, or features like the promiscous mode or the max receive frame lenght may be set programming some of the CSRs properly. Pointers to both the Transmit Buffer Descriptors ring (TBD) and theReceive Buffer Descriptors ring (RBD) are also stored in the CSRs.The CSRs are located in on-chip RAM and must be accessed using the big-endian mode.<p>The BDs are used to pass data buffers and related buffer informationbetween the hardware and the software. They reside in the host main memory and basically include local status information and a pointerto the actual buffer, again in external memory.<p>This driver must be given several target-specific parameters, and some external support routines must be provided. These parameters, and the mechanisms used to communicate them to the driver, are detailed below.<p></blockquote><h4>BOARD LAYOUT</h4><blockquote><p>This device is on-board. No jumpering diagram is necessary.<p></blockquote><h4>EXTERNAL INTERFACE</h4><blockquote><p><p>The driver provides the standard external interface, <b><i><a href="./motFecEnd.html#motFecEndLoad">motFecEndLoad</a></i>( )</b>, whichtakes a string of colon-separated parameters. The parameters should bespecified in hexadecimal, optionally preceeded by "0x" or a minus sign "-".<p>The parameter string is parsed using <b><i><a href="./ansiString.html#strtok_r">strtok_r</a></i>( )</b> and each parameter isconverted from a string representation to binary by a call tostrtoul(parameter, NULL, 16).<p>The format of the parameter string is:<p>"<i>motCpmAddr</i>:<i>ivec</i>:<i>bufBase</i>:<i>bufSize</i>:<i>fifoTxBase</i>:<i>fifoRxBase</i>:<i>tbdNum</i>:<i>rbdNum</i>:<i>phyAddr</i>:<i>isoPhyAddr</i>:<i>phyDefMode</i>:<i>userFlags</i>"<p></blockquote><h4>TARGET-SPECIFIC PARAMETERS</h4><blockquote><p><p><dl><dt><i>motCpmAddr</i><dd>Indicates the address at which the host processor presents its internal memory (also known as the dual ported RAM base address). With this address, the driver is able to compute the location of the FEC parameter RAM, and, ultimately, to program the FEC for proper operations. <p><dt><i>ivec</i><dd>This driver configures the host processor to generate hardware interruptsfor various events within the device. The interrupt-vector offsetparameter is used to connect the driver's ISR to the interrupt througha call to the VxWorks system function <b><i><a href="./intArchLib.html#intConnect">intConnect</a></i>( )</b>. It is also used tocompute the interrupt level (0-7) associated with the FEC interrupt (oneof the MPC860T SIU internal interrupt sources). The latter is given asa parameter to <b><i><a href="./intArchLib.html#intEnable">intEnable</a></i>( )</b>, in order to enable this level interrupt tothe PPC core.<p><dt><i>bufBase</i><dd>The Motorola Fast Ethernet Controller is a DMA-type device and typically shares access to some region of memory with the CPU. This driver is designedfor systems that directly share memory between the CPU and the FEC.<p>This parameter tells the driver that space for the both the TBDs and the RBDs needs not be allocated but should be taken from a cache-coherent private memory space provided by the user at the given address. The user should be aware that memory used for buffers descriptors must be 8-byte aligned and non-cacheable. All the buffer descriptors should fit in the given memory space. <p>If this parameter is "NONE", space for buffer descriptors is obtained by calling <b><i><a href="./cacheLib.html#cacheDmaMalloc">cacheDmaMalloc</a></i>( )</b> in <b><i><a href="./motFecEnd.html#motFecEndLoad">motFecEndLoad</a></i>( )</b>.<p><dt><i>bufSize</i><dd>The memory size parameter specifies the size of the pre-allocated memoryregion. If <i>bufBase</i> is specified as NONE (-1), the driver ignores thisparameter. Otherwise, the driver checks the size of the provided memory region is adequate with respect to the given number of Transmit BufferDescriptors and Receive Buffer Descriptors.<p><dt><i>fifoTxBase</i><dd>Indicate the base location of the transmit FIFO, in internal memory.The user does not need to initialize this parameter, as the related FEC register defaults to a proper value after reset. The specificreset value is microcode dependent. However, if the user wishes to reserve some RAM for other purposes, he may set this parameter to a different value. This should not be less than the default.<p>If <i>fifoTxBase</i> is specified as NONE (-1), the driver ignores it.<p><dt><i>fifoRxBase</i><dd>Indicate the base location of the receive FIFO, in internal memory.The user does not need to initialize this parameter, as the related FEC register defaults to a proper value after reset. The specificreset value is microcode dependent. However, if the user wishes to reserve some RAM for other purposes, he may set this parameter to a different value. This should not be less than the default.<p>If <i>fifoRxBase</i> is specified as NONE (-1), the driver ignores it.<p><dt><i>tbdNum</i><dd>This parameter specifies the number of transmit buffer descriptors (TBDs). Each buffer descriptor resides in 8 bytes of the processor's externalRAM space, and each one points to a 1536-byte buffer again in external RAM. If this parameter is less than a minimum number specified in the macro <b>MOT_FEC_TBD_MIN</b>, or if it is "NULL", a default value of 64 is used. This default number is kept deliberately hugh, since each packet the driver sends may consume more than a single TBD. This parameter should always equal a even number.<p><dt><i>rbdNum</i><dd>This parameter specifies the number of receive buffer descriptors (RBDs). Each buffer descriptor resides in 8 bytes of the processor's externalRAM space, and each one points to a 1536-byte buffer again in external RAM. If this parameter is less than a minimum number specified in the macro <b>MOT_FEC_RBD_MIN</b>, or if it is "NULL", a default value of 48 is used. This parameter should always equal a even number.<p><dt><i>phyAddr</i><dd>This parameter specifies the logical address of a MII-compliant physicaldevice (PHY) that is to be used as a physical media on the network.Valid addresses are in the range 0-31. There may be more than one deviceunder the control of the same management interface. If this parameter is "NULL", the default physical layer initialization routine will find out the PHY actual address by scanning the whole range. The one with the lowestaddress will be chosen.<p><dt><i>isoPhyAddr</i><dd>This parameter specifies the logical address of a MII-compliant physicaldevice (PHY) that is to be electrically isolated by the management interface. Valid addresses are in the range 0-31. If this parameter equals 0xff, the default physical layer initialization routine will assume there is no need to isolate any device. However, this parameter will be ignored unless the <b>MOT_FEC_USR_PHY_ISO</b> bit in the <i>userFlags</i>is set to one.<p><dt><i>phyDefMode</i><dd>This parameter specifies the operating mode that will be set upby the default physical layer initialization routine in case allthe attempts made to establish a valid link failed. If that happens,the first PHY that matches the specified abilities will be chosen towork in that mode, and the physical link will not be tested.<p><dt><i>userFlags</i><dd>This field enables the user to give some degree of customization to thedriver, especially as regards the physical layer interface.<p><b>MOT_FEC_USR_PHY_NO_AN</b>: the default physical layer initializationroutine will exploit the auto-negotiation mechanism as described inthe IEEE Std 802.3, to bring a valid link up. According to it, allthe link partners on the media will take part to the negotiationprocess, and the highest priority common denominator technology abilitywill be chosen. It the user wishes to prevent auto-negotiation fromoccurring, he may set this bit in the user flags.<p><b>MOT_FEC_USR_PHY_TBL</b>: in the auto-negotiation process, PHYsadvertise all their technology abilities at the same time,and the result is that the maximum common denominator is used. However,this behaviour may be changed, and the user may affect the order howeach subset of PHY's abilities is negotiated. Hence, when the<b>MOT_FEC_USR_PHY_TBL</b> bit is set, the default physical layerinitialization routine will look at the motFecPhyAnOrderTbl[] table andauto-negotiate a subset of abilities at a time, as suggested by thetable itself. It is worth noticing here, however, that if the⌨️ 快捷键说明
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