intarchlib.html

vxworks相关论文

    FUNCPTR * baseAddr /* new vector (trap) base address */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine sets the vector (trap) base address.  The CPU's vector base
register is set to the specified value, and subsequent calls to <b><i><a href="./intArchLib.html#intVecGet">intVecGet</a></i>(&nbsp;)</b>
or <b><i><a href="./intArchLib.html#intVecSet">intVecSet</a></i>(&nbsp;)</b> will use this base address.  The vector base address is
initially 0 (0x1000 for SPARC), until modified by calls to this routine.
<p>
</blockquote><h4>NOTE SPARC</h4><blockquote><p>
<p>
On SPARC processors, the vector base address must be on a 4 Kbyte boundary
(that is, its bottom 12 bits must be zero).
<p>
</blockquote><h4>NOTE 68000</h4><blockquote><p>
<p>
The 68000 has no vector base register; thus, this routine is a no-op for
68000 systems.
<p>
</blockquote><h4>NOTE I960</h4><blockquote><p>
<p>
This routine is a no-op for i960 systems.  The interrupt vector table is
located in <b><a href="./sysLib.html#top">sysLib</a></b>, and moving it by <b><i><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a></i>(&nbsp;)</b> would require
resetting the processor.  Also, the vector base is cached on-chip in the
PRCB and thus cannot be set from this routine.
<p>
</blockquote><h4>NOTE MIPS</h4><blockquote><p>
<p>
The MIPS processors have no vector base register;
thus this routine is a no-op for this architecture.
<p>
</blockquote><h4>NOTE ARM</h4><blockquote><p>
<p>
The ARM processors have no vector base register;
thus this routine is a no-op for this architecture.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
N/A
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><i><a href="./intArchLib.html#intVecBaseGet">intVecBaseGet</a></i>(&nbsp;)</b>, <b><i><a href="./intArchLib.html#intVecGet">intVecGet</a></i>(&nbsp;)</b>, <b><i><a href="./intArchLib.html#intVecSet">intVecSet</a></i>(&nbsp;)</b>

<hr>
<a name="intVecBaseGet"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intVecBaseGet</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intVecBaseGet</i>(&nbsp;)</strong> - get the vector (trap) base address (MC680x0, SPARC, i960, x86, MIPS, ARM)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>

FUNCPTR *intVecBaseGet (void)</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine returns the current vector base address, which is set
with <b><i><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a></i>(&nbsp;)</b>.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
The current vector base address (i960 = value of <b>sysIntTable</b>
set in <b><a href="./sysLib.html#top">sysLib</a></b>, MIPS = 0 always, ARM = 0 always).
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><i><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a></i>(&nbsp;)</b>

<hr>
<a name="intVecSet"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intVecSet</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intVecSet</i>(&nbsp;)</strong> - set a CPU vector (trap) (MC680x0, SPARC, i960, x86, MIPS)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void intVecSet
    (
    FUNCPTR * vector,  /* vector offset */
    FUNCPTR   function /* address to place in vector */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine attaches an exception/interrupt/trap handler to a specified 
vector.  The vector is specified as an offset into the CPU's vector table. 
This vector table starts, by default, at:
<p>
<table>
<tr valign=top>
<td align=left>    MC680x0:     </td><td align=left> 0</tr>
<tr valign=top>
<td align=left>    SPARC:       </td><td align=left> 0x1000</tr>
<tr valign=top>
<td align=left>    i960:        </td><td align=left> <b>sysIntTable</b> in sysLib</tr>
<tr valign=top>
<td align=left>    MIPS:        </td><td align=left> <b>excBsrTbl</b> in excArchLib</tr>
<tr valign=top>
<td align=left>    i386/i486:   </td><td align=left> 0</tr>
<tr valign=top>
<td align=left></tr>
</tr>

</table>

However, the vector table may be set to start at any address with
<b><i><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a></i>(&nbsp;)</b> (on CPUs for which it is available).  The vector table is
set up in <b><i><a href="./usrConfig.html#usrInit">usrInit</a></i>(&nbsp;)</b>.
<p>
This routine takes an interrupt vector as a parameter, which is the byte
offset into the vector table. Macros are provided to convert between interrupt
vectors and interrupt numbers, see <b><a href="./intArchLib.html#top">intArchLib</a></b>.
<p>
</blockquote><h4>NOTE SPARC</h4><blockquote><p>
<p>
This routine generates code to:
<dl>
<dt>
(1)
<dd>

save volatile registers;
<p>
<dt>
(2)
<dd>

fix possible window overflow;
<p>
<dt>
(3)
<dd>

read the processor state register into register %L0; and 
<p>
<dt>
(4)
<dd>
 jump to the specified address. 
</dl>

<p>

The <b><i><a href="./intArchLib.html#intVecSet">intVecSet</a></i>(&nbsp;)</b> routine puts this generated code into the trap table
entry corresponding to <i>vector</i>.
<p>
Window overflow and window underflow are sacred to
the kernel and may not be pre-empted.  They are written here
only to track changing trap base registers (TBRs).
With the "branch anywhere" scheme (as opposed to the branch PC-relative
+/-8 megabytes) the first instruction in the vector table must not be a 
change of flow control nor affect any critical registers.  The JMPL that 
replaces the BA will always execute the next vector's first instruction.
<p>
</blockquote><h4>NOTE I960</h4><blockquote><p>
<p>
Vectors 0-7 are illegal vectors; using them puts the vector into the
priorities/pending portion of the table, which yields undesirable
actions.  The i960CA caches the NMI vector in internal RAM at system
power-up.  This is where the vector is taken when the NMI occurs.  Thus, it
is important to check to see if the vector being changed is the NMI
vector, and, if so, to write it to internal RAM.
<p>
</blockquote><h4>NOTE MIPS</h4><blockquote><p>
<p>
On MIPS CPUs the vector table is set up statically in software.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
N/A
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><i><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a></i>(&nbsp;)</b>, <b><i><a href="./intArchLib.html#intVecGet">intVecGet</a></i>(&nbsp;)</b>

<hr>
<a name="intVecGet"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intVecGet</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intVecGet</i>(&nbsp;)</strong> - get an interrupt vector (MC680x0, SPARC, i960, x86, MIPS)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>FUNCPTR intVecGet
    (
    FUNCPTR * vector /* vector offset */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine returns a pointer to the exception/interrupt handler attached
to a specified vector.  The vector is specified as an offset into the CPU's
vector table.  This vector table starts, by default, at:
<p>
<table>
<tr valign=top>
<td align=left>    MC680x0:     </td><td align=left> 0</tr>
<tr valign=top>
<td align=left>    SPARC:       </td><td align=left> 0x1000</tr>
<tr valign=top>
<td align=left>    i960:        </td><td align=left> <b>sysIntTable</b> in sysLib</tr>
<tr valign=top>
<td align=left>    MIPS:        </td><td align=left> <b>excBsrTbl</b> in excArchLib</tr>
<tr valign=top>
<td align=left>    i386/i486:   </td><td align=left> 0</tr>
<tr valign=top>
<td align=left></tr>
</tr>

</table>

However, the vector table may be set to start at any address with
<b><i><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a></i>(&nbsp;)</b> (on CPUs for which it is available).
<p>
This routine takes an interrupt vector as a parameter, which is the byte
offset into the vector table. Macros are provided to convert between interrupt
vectors and interrupt numbers, see <b><a href="./intArchLib.html#top">intArchLib</a></b>.
<p>
</blockquote><h4>NOTE I960</h4><blockquote><p>
<p>
The interrupt table location is reinitialized to <i>sysIntTable</i> after
booting.  This location is returned by <b><i><a href="./intArchLib.html#intVecBaseGet">intVecBaseGet</a></i>(&nbsp;)</b>.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
<p>
A pointer to the exception/interrupt handler attached to the specified vector.
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><i><a href="./intArchLib.html#intVecSet">intVecSet</a></i>(&nbsp;)</b>, <b><i><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a></i>(&nbsp;)</b>

<hr>
<a name="intVecTableWriteProtect"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intVecTableWriteProtect</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intVecTableWriteProtect</i>(&nbsp;)</strong> - write-protect exception vector table (MC680x0, SPARC, i960, x86, ARM)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>

STATUS intVecTableWriteProtect (void)</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
If the unbundled Memory Management Unit (MMU) support package (VxVMI) is
present, this routine write-protects the exception vector table to
protect it from being accidentally corrupted.
<p>
Note that other data structures contained in the page will also be 
write-protected.  In the default VxWorks configuration, the exception vector
table is located at location 0 in memory.  Write-protecting this affects
the backplane anchor, boot configuration information, and potentially the
text segment (assuming the default text location of 0x1000.)  All code
that manipulates these structures has been modified to write-enable 
memory for the duration of the operation.  If you select a different
address for the exception vector table, be sure it resides in a page
separate from other writable data structures.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK, or ERROR if memory cannot be write-protected.
<p>
</blockquote><h4>ERRNO</h4><blockquote><p>
S_intLib_VEC_TABLE_WP_UNAVAILABLE
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intUninitVecSet"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intUninitVecSet</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intUninitVecSet</i>(&nbsp;)</strong> - set the uninitialized vector handler (ARM)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void intUninitVecSet
    (
    VOIDFUNCPTR routine /* ptr to user routine */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine installs a handler for the uninitialized vectors to be
called when any uninitialised vector is entered.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
N/A.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

</body>
</html>