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</blockquote><h4>NOTE ARM</h4><blockquote><p>
<p>
ARM processors generally do not have on-chip interrupt controllers.
Control of interrupts is a BSP-specific matter.  This routine calls a
BSP-specific routine to enable the interrupt.  For each interrupt
level to be used, there must be a call to this routine before it will
be allowed to interrupt.
<p>
</blockquote><h4>NOTE MIPS</h4><blockquote><p>
<p>
For MIPS, it is strongly advised that the level be a combination of
<b>SR_IBIT1</b> - <b>SR_IBIT8</b>.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK or ERROR. (MIPS: The previous contents of the status register).
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intDisable"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intDisable</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intDisable</i>(&nbsp;)</strong> - disable corresponding interrupt bits (MIPS, PowerPC, ARM)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>int intDisable
    (
    int level /* new interrupt bits (0x0 - 0xff00) */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
On MIPS and PowerPC architectures, this routine disables the corresponding
interrupt bits from the present status register.  
<p>
</blockquote><h4>NOTE ARM</h4><blockquote><p>
<p>
ARM processors generally do not have on-chip interrupt controllers.
Control of interrupts is a BSP-specific matter. This routine calls a
BSP-specific routine to disable a particular interrupt level,
regardless of the current interrupt mask level.
<p>
</blockquote><h4>NOTE MIPS</h4><blockquote><p>
<p>
For MIPS, the macros <b>SR_IBIT1</b> - <b>SR_IBIT8</b> define bits that may be set.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK or ERROR. (MIPS: The previous contents of the status register).
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intCRGet"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intCRGet</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intCRGet</i>(&nbsp;)</strong> - read the contents of the cause register (MIPS)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>

int intCRGet (void)</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine reads and returns the contents of the MIPS cause
register.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
The contents of the cause register.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intCRSet"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intCRSet</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intCRSet</i>(&nbsp;)</strong> - write the contents of the cause register (MIPS)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void intCRSet
    (
    int value /* value to write to cause register */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine writes the contents of the MIPS cause register.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
N/A
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intSRGet"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intSRGet</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intSRGet</i>(&nbsp;)</strong> - read the contents of the status register (MIPS)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>

int intSRGet (void)</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine reads and returns the contents of the MIPS status
register.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
The previous contents of the status register.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intSRSet"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intSRSet</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intSRSet</i>(&nbsp;)</strong> - update the contents of the status register (MIPS)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>int intSRSet
    (
    int value /* value to write to status register */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine updates and returns the previous contents of the MIPS
status register.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
The previous contents of the status register.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intConnect"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intConnect</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intConnect</i>(&nbsp;)</strong> - connect a C routine to a hardware interrupt</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>STATUS intConnect
    (
    VOIDFUNCPTR * vector,   /* interrupt vector to attach to */
    VOIDFUNCPTR   routine,  /* routine to be called */
    int           parameter /* parameter to be passed to routine */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine connects a specified C routine to a specified interrupt
vector.  The address of <i>routine</i> is generally stored at <i>vector</i> so
that <i>routine</i> is called with <i>parameter</i> when the interrupt occurs.
The routine is invoked in supervisor mode at interrupt level.  A proper
C environment is established, the necessary registers saved, and the
stack set up.
<p>
The routine can be any normal C code, except that it must not invoke
certain operating system functions that may block or perform I/O
operations.
<p>
This routine generally simply calls <b><i><a href="./intArchLib.html#intHandlerCreate">intHandlerCreate</a></i>(&nbsp;)</b> and
<b><i><a href="./intArchLib.html#intVecSet">intVecSet</a></i>(&nbsp;)</b>.  The address of the handler returned by <b><i><a href="./intArchLib.html#intHandlerCreate">intHandlerCreate</a></i>(&nbsp;)</b>
is what actually goes in the interrupt vector.
<p>
This routine takes an interrupt vector as a parameter, which is the byte
offset into the vector table. Macros are provided to convert between interrupt
vectors and interrupt numbers, see <b><a href="./intArchLib.html#top">intArchLib</a></b>.
<p>
</blockquote><h4>NOTE ARM</h4><blockquote><p>
<p>
ARM processors generally do not have on-chip interrupt controllers.
Control of interrupts is a BSP-specific matter. This routine calls a
BSP-specific routine to install the handler such that, when the
interrupt occurs, <i>routine</i> is called with <i>parameter</i>.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
OK, or ERROR if the interrupt handler cannot be built.
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><i><a href="./intArchLib.html#intHandlerCreate">intHandlerCreate</a></i>(&nbsp;)</b>, <b><i><a href="./intArchLib.html#intVecSet">intVecSet</a></i>(&nbsp;)</b>

<hr>
<a name="intHandlerCreate"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intHandlerCreate</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intHandlerCreate</i>(&nbsp;)</strong> - construct an interrupt handler for a C routine (MC680x0, SPARC, i960, x86, MIPS)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>FUNCPTR intHandlerCreate
    (
    FUNCPTR routine,  /* routine to be called */
    int     parameter /* parameter to be passed to routine */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine builds an interrupt handler around the specified C routine.
This interrupt handler is then suitable for connecting to a specific
vector address with <b><i><a href="./intArchLib.html#intVecSet">intVecSet</a></i>(&nbsp;)</b>.  The interrupt handler is invoked in
supervisor mode at interrupt level.  A proper C environment is
established, the necessary registers saved, and the stack set up.
<p>
The routine can be any normal C code, except that it must not invoke
certain operating system functions that may block or perform I/O
operations.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
A pointer to the new interrupt handler, or NULL if memory 
is insufficient.
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>

<hr>
<a name="intLockLevelSet"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intLockLevelSet</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intLockLevelSet</i>(&nbsp;)</strong> - set the current interrupt lock-out level (MC680x0, SPARC, i960, x86, ARM)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void intLockLevelSet
    (
    int newLevel /* new interrupt level */
    )</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine sets the current interrupt lock-out level and stores it
in the globally accessible variable <b>intLockMask</b>.  The specified
interrupt level is masked when interrupts are locked by
<b><i><a href="./intArchLib.html#intLock">intLock</a></i>(&nbsp;)</b>.  The default lock-out level (MC680x0 = 7, SPARC = 15,
i960 = 31, i386/i486 = 1) is initially set by <b><i><a href="./kernelLib.html#kernelInit">kernelInit</a></i>(&nbsp;)</b> when
VxWorks is initialized.
<p>
</blockquote><h4>NOTE ARM</h4><blockquote><p>
<p>
On the ARM, this call establishes the interrupt level to be set when
<b><i><a href="./intArchLib.html#intLock">intLock</a></i>(&nbsp;)</b> is called.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
N/A
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><i><a href="./intArchLib.html#intLockLevelGet">intLockLevelGet</a></i>(&nbsp;)</b>, <b><i><a href="./intArchLib.html#intLock">intLock</a></i>(&nbsp;)</b>, <b><i><a href="./taskLib.html#taskLock">taskLock</a></i>(&nbsp;)</b>

<hr>
<a name="intLockLevelGet"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intLockLevelGet</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intLockLevelGet</i>(&nbsp;)</strong> - get the current interrupt lock-out level (MC680x0, SPARC, i960, x86, ARM)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>

int intLockLevelGet (void)</pre>

</blockquote><h4>DESCRIPTION</h4><blockquote><p>
This routine returns the current interrupt lock-out level, which is
set by <b><i><a href="./intArchLib.html#intLockLevelSet">intLockLevelSet</a></i>(&nbsp;)</b> and stored in the globally accessible
variable <b>intLockMask</b>.  This is the interrupt level currently
masked when interrupts are locked out by <b><i><a href="./intArchLib.html#intLock">intLock</a></i>(&nbsp;)</b>.  The default
lock-out level (MC680x0 = 7, SPARC = 15, i960 = 31, i386/i486 = 1)
is initially set by <b><i><a href="./kernelLib.html#kernelInit">kernelInit</a></i>(&nbsp;)</b> when VxWorks is initialized.
<p>
</blockquote><h4>RETURNS</h4><blockquote><p>
The interrupt level currently stored in the interrupt
lock-out mask. (ARM = ERROR always)
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./intArchLib.html#top">intArchLib</a></b>, <b><i><a href="./intArchLib.html#intLockLevelSet">intLockLevelSet</a></i>(&nbsp;)</b>

<hr>
<a name="intVecBaseSet"></a>
<p align=right>
<a href="rtnIndex.html"><i>Libraries :  Routines</i></a></p>

</blockquote><h1><i>intVecBaseSet</i>(&nbsp;)</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote>  
<p><strong><i>intVecBaseSet</i>(&nbsp;)</strong> - set the vector (trap) base address (MC680x0, SPARC, i960, x86, MIPS, ARM)</p>

</blockquote><h4>SYNOPSIS</h4><blockquote><p>
<pre>void intVecBaseSet
    (