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g0 {return the contents of register `g0', also `g1' - `g7' (SPARC) and `g1' - `g14' (i960)} {<b><i>g0</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#g0">g0</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
a0 {return the contents of register `a0' (also `a1' - `a7') (MC680x0)} {<b><i>a0</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#a0">a0</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
d0 {return the contents of register `d0' (also `d1' - `d7') (MC680x0)} {<b><i>d0</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#d0">d0</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
sr {return the contents of the status register (MC680x0)} {<b><i>sr</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#sr">sr</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
psrShow {display the meaning of a specified `psr' value, symbolically (SPARC)} {<b><i>psrShow</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#psrShow">psrShow</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
fsrShow {display the meaning of a specified fsr value, symbolically (SPARC)} {<b><i>fsrShow</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#fsrShow">fsrShow</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
o0 {return the contents of register `o0' (also `o1' - `o7') (SPARC)} {<b><i>o0</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#o0">o0</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
l0 {return the contents of register `l0' (also `l1' - `l7') (SPARC)} {<b><i>l0</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#l0">l0</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
i0 {return the contents of register `i0' (also `i1' - `i7') (SPARC)} {<b><i>i0</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#i0">i0</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
npc {return the contents of the next program counter (SPARC)} {<b><i>npc</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#npc">npc</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
psr {return the contents of the processor status register (SPARC)} {<b><i>psr</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#psr">psr</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
wim {return the contents of the window invalid mask register (SPARC)} {<b><i>wim</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#wim">wim</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
y {return the contents of the `y' register (SPARC)} {<b><i>y</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#y">y</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
pfp {return the contents of register `pfp' (i960)} {<b><i>pfp</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#pfp">pfp</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
tsp {return the contents of register `sp' (i960)} {<b><i>tsp</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#tsp">tsp</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
rip {return the contents of register `rip' (i960)} {<b><i>rip</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#rip">rip</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
r3 {return the contents of register `r3' (also `r4' - `r15') (i960)} {<b><i>r3</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#r3">r3</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
fp {return the contents of register `fp' (i960)} {<b><i>fp</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#fp">fp</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
fp0 {return the contents of register `fp0' (also `fp1' - `fp3') (i960KB, i960SB)} {<b><i>fp0</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#fp0">fp0</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
pcw {return the contents of the `pcw' register (i960)} {<b><i>pcw</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#pcw">pcw</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
tcw {return the contents of the `tcw' register (i960)} {<b><i>tcw</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#tcw">tcw</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
acw {return the contents of the `acw' register (i960)} {<b><i>acw</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#acw">acw</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
dbgBpTypeBind {bind a breakpoint handler to a breakpoint type (MIPS R3000, R4000)} {<b><i>dbgBpTypeBind</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#dbgBpTypeBind">dbgBpTypeBind</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
edi {return the contents of register `edi' (also `esi' - `eax') (i386/i486)} {<b><i>edi</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#edi">edi</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
eflags {return the contents of the status register (i386/i486)} {<b><i>eflags</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#eflags">eflags</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
r0 {return the contents of register `r0' (also `r1' - `r14') (ARM)} {<b><i>r0</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#r0">r0</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
cpsr {return the contents of the current processor status register (ARM)} {<b><i>cpsr</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#cpsr">cpsr</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
psrShow {display the meaning of a specified PSR value, symbolically (ARM)} {<b><i>psrShow;1</i>\(&nbsp;\)</b>} {<b><i><a href="./dbgArchLib.html#psrShow_1">psrShow</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
excVecInit {initialize the exception/interrupt vectors} {<b><i>excVecInit</i>\(&nbsp;\)</b>} {<b><i><a href="./excArchLib.html#excVecInit">excVecInit</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
excConnect {connect a C routine to an exception vector (PowerPC)} {<b><i>excConnect</i>\(&nbsp;\)</b>} {<b><i><a href="./excArchLib.html#excConnect">excConnect</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
excIntConnect {connect a C routine to an asynchronous exception vector (PowerPC, ARM)} {<b><i>excIntConnect</i>\(&nbsp;\)</b>} {<b><i><a href="./excArchLib.html#excIntConnect">excIntConnect</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
excCrtConnect {connect a C routine to a critical exception vector (PowerPC 403)} {<b><i>excCrtConnect</i>\(&nbsp;\)</b>} {<b><i><a href="./excArchLib.html#excCrtConnect">excCrtConnect</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
excIntCrtConnect {connect a C routine to a critical interrupt vector (PowerPC 403)} {<b><i>excIntCrtConnect</i>\(&nbsp;\)</b>} {<b><i><a href="./excArchLib.html#excIntCrtConnect">excIntCrtConnect</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
excVecSet {set a CPU exception vector (PowerPC, ARM)} {<b><i>excVecSet</i>\(&nbsp;\)</b>} {<b><i><a href="./excArchLib.html#excVecSet">excVecSet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
excVecGet {get a CPU exception vector (PowerPC, ARM)} {<b><i>excVecGet</i>\(&nbsp;\)</b>} {<b><i><a href="./excArchLib.html#excVecGet">excVecGet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
fppSave {save the floating-point coprocessor context} {<b><i>fppSave</i>\(&nbsp;\)</b>} {<b><i><a href="./fppArchLib.html#fppSave">fppSave</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
fppRestore {restore the floating-point coprocessor context} {<b><i>fppRestore</i>\(&nbsp;\)</b>} {<b><i><a href="./fppArchLib.html#fppRestore">fppRestore</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
fppProbe {probe for the presence of a floating-point coprocessor} {<b><i>fppProbe</i>\(&nbsp;\)</b>} {<b><i><a href="./fppArchLib.html#fppProbe">fppProbe</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
fppTaskRegsGet {get the floating-point registers from a task TCB} {<b><i>fppTaskRegsGet</i>\(&nbsp;\)</b>} {<b><i><a href="./fppArchLib.html#fppTaskRegsGet">fppTaskRegsGet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
fppTaskRegsSet {set the floating-point registers of a task} {<b><i>fppTaskRegsSet</i>\(&nbsp;\)</b>} {<b><i><a href="./fppArchLib.html#fppTaskRegsSet">fppTaskRegsSet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intLevelSet {set the interrupt level (MC680x0, SPARC, i960, x86, ARM)} {<b><i>intLevelSet</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intLevelSet">intLevelSet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intLock {lock out interrupts} {<b><i>intLock</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intLock">intLock</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intUnlock {cancel interrupt locks} {<b><i>intUnlock</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intUnlock">intUnlock</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intEnable {enable corresponding interrupt bits (MIPS, PowerPC, ARM)} {<b><i>intEnable</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intEnable">intEnable</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intDisable {disable corresponding interrupt bits (MIPS, PowerPC, ARM)} {<b><i>intDisable</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intDisable">intDisable</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intCRGet {read the contents of the cause register (MIPS)} {<b><i>intCRGet</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intCRGet">intCRGet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intCRSet {write the contents of the cause register (MIPS)} {<b><i>intCRSet</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intCRSet">intCRSet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intSRGet {read the contents of the status register (MIPS)} {<b><i>intSRGet</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intSRGet">intSRGet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intSRSet {update the contents of the status register (MIPS)} {<b><i>intSRSet</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intSRSet">intSRSet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intConnect {connect a C routine to a hardware interrupt} {<b><i>intConnect</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intConnect">intConnect</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intHandlerCreate {construct an interrupt handler for a C routine (MC680x0, SPARC, i960, x86, MIPS)} {<b><i>intHandlerCreate</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intHandlerCreate">intHandlerCreate</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intLockLevelSet {set the current interrupt lock-out level (MC680x0, SPARC, i960, x86, ARM)} {<b><i>intLockLevelSet</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intLockLevelSet">intLockLevelSet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intLockLevelGet {get the current interrupt lock-out level (MC680x0, SPARC, i960, x86, ARM)} {<b><i>intLockLevelGet</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intLockLevelGet">intLockLevelGet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intVecBaseSet {set the vector (trap) base address (MC680x0, SPARC, i960, x86, MIPS, ARM)} {<b><i>intVecBaseSet</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intVecBaseSet">intVecBaseSet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intVecBaseGet {get the vector (trap) base address (MC680x0, SPARC, i960, x86, MIPS, ARM)} {<b><i>intVecBaseGet</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intVecBaseGet">intVecBaseGet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intVecSet {set a CPU vector (trap) (MC680x0, SPARC, i960, x86, MIPS)} {<b><i>intVecSet</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intVecSet">intVecSet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intVecGet {get an interrupt vector (MC680x0, SPARC, i960, x86, MIPS)} {<b><i>intVecGet</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intVecGet">intVecGet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intVecTableWriteProtect {write-protect exception vector table (MC680x0, SPARC, i960, x86, ARM)} {<b><i>intVecTableWriteProtect</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intVecTableWriteProtect">intVecTableWriteProtect</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
intUninitVecSet {set the uninitialized vector handler (ARM)} {<b><i>intUninitVecSet</i>\(&nbsp;\)</b>} {<b><i><a href="./intArchLib.html#intUninitVecSet">intUninitVecSet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}
taskSRSet {set the task status register (MC680x0, MIPS, i386/i486)} {<b><i>taskSRSet</i>\(&nbsp;\)</b>} {<b><i><a href="./taskArchLib.html#taskSRSet">taskSRSet</a></i>(\&nbsp;)</b>} {VxWorks Reference Manual} Libraries {} {}