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<html><head><!-- /vobs/wpwr/docs/vxworks/ref/if_lnPci.html - generated by refgen from if_lnPci.c --> <title> if_lnPci </title></head><body bgcolor="#FFFFFF"> <hr><a name="top"></a><p align=right><a href="libIndex.html"><i>VxWorks Reference Manual : Libraries</i></a></p></blockquote><h1>if_lnPci</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>if_lnPci</strong> - AMD Am79C970 PCnet-PCI Ethernet network interface driver </p></blockquote><h4>ROUTINES</h4><blockquote><p><p><b><i><a href="./if_lnPci.html#lnPciattach">lnPciattach</a></i>( )</b> - publish the <b>lnPci</b> network interface and initialize the driver and device<br><p></blockquote><h4>DESCRIPTION</h4><blockquote><p>This module implements the Advanced Micro Devices Am79C970 PCnet-PCIEthernet 32 bit network interface driver.<p>The PCnet-PCI ethernet controller is inherently little endian becausethe chip is designed to operate on a PCI bus which is a little endianbus. The software interface to the driver is divided into three parts.The first part is the PCI configuration registers and their set up. This part is done at the BSP level in the various BSPs which use thisdriver. The second and third part are dealt in the driver. The secondpart of the interface comprises of the I/O control registers and theirprogramming. The third part of the interface comprises of the descriptorsand the buffers. <p>This driver is designed to be moderately generic, operating unmodifiedacross the range of architectures and targets supported by VxWorks. Toachieve this, the driver must be given several target-specific parameters,and some external support routines must be provided. These parameters,and the mechanisms used to communicate them to the driver, are detailedbelow. If any of the assumptions stated below are not true for yourparticular hardware, this driver will probably not function correctly withit.<p>This driver supports only one LANCE unit per CPU. The driver can beconfigured to support big-endian or little-endian architectures. It<p>contains error recovery code to handle known device errata related to DMAactivity. <p>Big endian processors can be connected to the PCI bus through some controllerswhich take care of hardware byte swapping. In such cases all the registers which the chip DMA s to have to be swapped and written to, so that when thehardware swaps the accesses, the chip would see them correctly. The chip stillhas to be programmed to operated in little endian mode as it is on the PCI bus.If the cpu board hardware automatically swaps all the accesses to and from thePCI bus, then input and output byte stream need not be swapped. <p></blockquote><h4>BOARD LAYOUT</h4><blockquote><p>This device is on-board. No jumpering diagram is necessary.<p></blockquote><h4>EXTERNAL INTERFACE</h4><blockquote><p>This driver provides the standard external interface with the followingexceptions. All initialization is performed within the attach routine;there is no separate initialization routine. Therefore, in the global interfacestructure, the function pointer to the initialization routine is NULL.<p>The only user-callable routine is <b><i><a href="./if_lnPci.html#lnPciattach">lnPciattach</a></i>( )</b>, which publishes the <b>lnPci</b>interface and initializes the driver and device.<p></blockquote><h4>TARGET-SPECIFIC PARAMETERS</h4><blockquote><p><dl><dt>bus mode<dd>This parameter is a global variable that can be modified at run-time.<p>The LANCE control register #3 determines the bus mode of the device,allowing the support of big-endian and little-endian architectures.This parameter, defined as "u_long lnPciCSR_3B", is the value that willbe placed into LANCE control register #3. The default value supportsMotorola-type buses. For information about changing this parameter, see the manual<i>Advanced Micro Devices Local Area Network Controller Am79C970 (PCnet-PCI). </i><p><dt>base address of device registers<dd>This parameter is passed to the driver by <b><i><a href="./if_lnPci.html#lnPciattach">lnPciattach</a></i>( )</b>. It indicates to the driver where to find the RDP register.<p>The LANCE presents two registers to the external interface, the RDP (registerdata port) and RAP (register address port) registers. This driver assumes that these two registers occupy two unique addresses in a memory spacethat is directly accessible by the CPU executing this driver. The driverassumes that the RDP register is mapped at a lower address than the RAPregister; the RDP register is therefore considered the "base address."<p><dt>interrupt vector<dd>This parameter is passed to the driver by <b><i><a href="./if_lnPci.html#lnPciattach">lnPciattach</a></i>( )</b>.<p>This driver configures the LANCE device to generate hardware interruptsfor various events within the device; thus it containsan interrupt handler routine. The driver calls <b><i><a href="./intArchLib.html#intConnect">intConnect</a></i>( )</b> to connect its interrupt handler to the interrupt vector generated as a result of the LANCE interrupt.<p><dt>interrupt level<dd>This parameter is passed to the driver by <b><i><a href="./if_lnPci.html#lnPciattach">lnPciattach</a></i>( )</b>.<p>Some targets use additional interrupt controller devices to help organize andservice the various interrupt sources. This driver avoids all board-specificknowledge of such devices. During the driver's initialization, the externalroutine <b><i><a href="../bsp/brutus/sysLib.html#sysLanIntEnable" >sysLanIntEnable</a></i>( )</b> is called to perform any board-specific operationsrequired to turn on LANCE interrupt generation. A similar routine,<b><i><a href="../bsp/brutus/sysLib.html#sysLanIntDisable" >sysLanIntDisable</a></i>( )</b>, is called by the driver before a LANCE reset to performboard-specific operations required to turn off LANCE interrupt generation.For a description of <b><i><a href="../bsp/brutus/sysLib.html#sysLanIntEnable" >sysLanIntEnable</a></i>( )</b>, and <b><i><a href="../bsp/brutus/sysLib.html#sysLanIntDisable" >sysLanIntDisable</a></i>( )</b>, see "ExternalSupport Requirements" below.<p>This parameter is passed to the external routine.<p><dt>shared memory address<dd>This parameter is passed to the driver by <b><i><a href="./if_lnPci.html#lnPciattach">lnPciattach</a></i>( )</b>.<p>The LANCE device is a DMA type of device and typically shares access tosome region of memory with the CPU. This driver is designed for systemsthat directly share memory between the CPU and the LANCE. Itassumes that this shared memory is directly available to itwithout any arbitration or timing concerns.<p>This parameter can be used to specify an explicit memory region for useby the LANCE. This should be done on hardware that restricts the LANCEto a particular memory region. The constant NONE can be used to indicatethat there are no memory limitations, in which case, the driver attempts to allocate the shared memory from the system space.<p><dt>shared memory size<dd>This parameter is passed to the driver by <b><i><a href="./if_lnPci.html#lnPciattach">lnPciattach</a></i>( )</b>.<p>This parameter can be used to explicitly limit the amount of sharedmemory (bytes) this driver will use. The constant NONE can be used toindicate no specific size limitation. This parameter is used only ifa specific memory region is provided to the driver.<p><dt>shared memory width<dd>This parameter is passed to the driver by <b><i><a href="./if_lnPci.html#lnPciattach">lnPciattach</a></i>( )</b>.<p>Some target hardware that restricts the shared memory region to aspecific location also restricts the access width to this region bythe CPU. On these targets, performing an access of an invalid widthwill cause a bus error.<p>This parameter can be used to specify the number of bytes of accesswidth to be used by the driver during access to the shared memory.The constant NONE can be used to indicate no restrictions.<p>Current internal support for this mechanism is not robust; implementation may not work on all targets requiring these restrictions.<p><dt>shared memory buffer size<dd>This parameter is passed to the driver by <b><i><a href="./if_lnPci.html#lnPciattach">lnPciattach</a></i>( )</b>.<p>The driver and LANCE device exchange network data in buffers. Thisparameter permits the size of these individual buffers to be limited.A value of zero indicates that the default buffer size should be used.The default buffer size is large enough to hold a maximum-size Ethernetpacket.<p>Use of this parameter should be rare. Network performancewill be affected, since the target will no longer be able to receiveall valid packet sizes.<p><dt>Ethernet address<dd>This parameter is obtained directly from a global memory location.<p>During initialization, the driver needs to know the Ethernet address forthe LANCE device. The driver assumes that this address is available ina global, six-byte character array, lnEnetAddr[]. This array istypically created and stuffed by the BSP code. </dl><p></blockquote><h4>EXTERNAL SUPPORT REQUIREMENTS</h4><blockquote><p>This driver requires one external support function:<dl><dt>void sysLanIntEnable (int level)<dd><p>This routine provides a target-specific enable of the interrupt for the LANCEdevice. Typically, this involves programming an interrupt controllerhardware, either internal or external to the CPU.<p>This routine is called during chip initialization, at startup and each LANCEdevice reset.<p><dt>void sysLanIntDisable (int level)<dd><p>This routine provides a target-specific disable of the interrupt for the LANCEdevice. Typically, this involves programming an interrupt controllerhardware, either internal or external to the CPU.<p>This routine is called before a LANCE device reset.<p></dl><p></blockquote><h4>SYSTEM RESOURCE USAGE</h4><blockquote><p>When implemented, this driver requires the following system resources:<p> - one mutual exclusion semaphore<br> - one interrupt vector<br> - 24 bytes in the initialized data section (data)<br> - 208 bytes in the uninitialized data section (BSS)<p>The above data and BSS requirements are for the MC68020 architecture and may vary for other architectures. Code size (text) varies greatly betweenarchitectures and is therefore not quoted here.<p>If the driver is not given a specific region of memory via the <b><i><a href="./if_lnPci.html#lnPciattach">lnPciattach</a></i>( )</b>routine, then it calls <b><i><a href="./cacheLib.html#cacheDmaMalloc">cacheDmaMalloc</a></i>( )</b> to allocate the memory to be shared with the LANCE. The size requested is 80,542 bytes. If a memory regionis provided to the driver, the size of this region is adjustable to suituser needs.<p>The LANCE can only be operated if the shared memory region is write-coherentwith the data cache. The driver cannot maintain cache coherencyfor the device for data that is written by the driver because fieldswithin the shared structures are asynchronously modified by both the driverand the device, and these fields may share the same cache line.<p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./if_lnPci.html#top">if_lnPci</a></b>, <b><a href="./ifLib.html#top">ifLib</a></b>, <i>Advanced Micro Devices PCnet-PCI Ethernet Controller for PCI. </i><hr><a name="lnPciattach"></a><p align=right><a href="rtnIndex.html"><i>Libraries : Routines</i></a></p></blockquote><h1><i>lnPciattach</i>( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong><i>lnPciattach</i>( )</strong> - publish the <b>lnPci</b> network interface and initialize the driver and device</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>STATUS lnPciattach ( int unit, /* unit number */ char * devAdrs, /* LANCE I/O address */ int ivec, /* interrupt vector */ int ilevel, /* interrupt level */ char * memAdrs, /* address of memory pool (-1 = malloc it) */ ULONG memSize, /* used if memory pool is NOT malloc()'d */ int memWidth, /* byte-width of data (-1 = any width) */ ULONG pciMemBase, /* memory base as seen from PCI */ int spare2 /* not used */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine publishes the <b>ln</b> interface by filling in a network interfacerecord and adding this record to the system list. This routine alsoinitializes the driver and the device to the operational state.<p>The <i>memAdrs</i> parameter can be used to specify the location of thememory that will be shared between the driver and the device. The valueNONE is used to indicate that the driver should obtain the memory.<p>The <i>memSize</i> parameter is valid only if the <i>memAdrs</i> parameter is notset to NONE, in which case <i>memSize</i> indicates the size of theprovided memory region.<p>The <i>memWidth</i> parameter sets the memory pool's data port width (in bytes);if it is NONE, any data width is used.<p></blockquote><h4>BUGS</h4><blockquote><p>To zero out LANCE data structures, this routine uses <b><i><a href="./bLib.html#bzero">bzero</a></i>( )</b>, whichignores the <i>memWidth</i> specification and uses any size data access towrite to memory.<p></blockquote><h4>RETURNS</h4><blockquote><p>OK or ERROR.</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./if_lnPci.html#top">if_lnPci</a></b></body></html>⌨️ 快捷键说明
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