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<html><head><!-- /vobs/wpwr/docs/vxworks/ref/cacheTiTms390Lib.html - generated by refgen from ../sparc/cacheTiTms390Lib.c --> <title> cacheTiTms390Lib </title></head><body bgcolor="#FFFFFF"> <hr><a name="top"></a><p align=right><a href="libIndex.html"><i>VxWorks Reference Manual : Libraries</i></a></p></blockquote><h1>cacheTiTms390Lib</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong>cacheTiTms390Lib</strong> - TI TMS390 SuperSPARC cache management library </p></blockquote><h4>ROUTINES</h4><blockquote><p><p><b><i><a href="./cacheTiTms390Lib.html#cacheTiTms390LibInit">cacheTiTms390LibInit</a></i>( )</b> - initialize the TI TMS390 cache library<br><b><i><a href="./cacheTiTms390Lib.html#cacheTiTms390VirtToPhys">cacheTiTms390VirtToPhys</a></i>( )</b> - translate a virtual address for <b><a href="./cacheLib.html#top">cacheLib</a></b><br><b><i><a href="./cacheTiTms390Lib.html#cacheTiTms390PhysToVirt">cacheTiTms390PhysToVirt</a></i>( )</b> - translate a physical address for drivers<br><b><i><a href="./cacheTiTms390Lib.html#cleanUpStoreBuffer">cleanUpStoreBuffer</a></i>( )</b> - clean up store buffer after a data store error interrupt<br><p></blockquote><h4>DESCRIPTION</h4><blockquote><p>This library contains architecture-specific cache library functions forthe TI TMS390 SuperSPARC architecture. The on-chip cache architecture isexplained in the first table below. Note, the data cache mode depends onwhether there is an external Multicache Controller (MCC). Bothon-chip caches support cache coherency via snooping and line locking.For memory allocation purposes, a cache line alignment size of 64 bytesis assumed. The MCC supports cache coherency via snooping, but doesnot support line locking.<p><table><tr valign=top><th align=left>Cache</th><th align=left> </th><th align=left> </th><th align=left> </th><th align=left> </th><th align=left>Line Size</th><th align=left> </tr><tr valign=top><th align=left>Type </th><th align=left>Size</th><th align=left>Lines</th><th align=left>Sets</th><th align=left>Ways</th><th align=left> (Bytes) </th><th align=left>Mode</tr><tr><td colspan="7"><hr></tr><tr valign=top><td align=left></tr><tr valign=top><td align=left>Instr</td><td align=left>20K </td><td align=left>320 </td><td align=left>64 </td><td align=left>5 </td><td align=left>2*32 </td><td align=left>never written back</tr><tr valign=top><td align=left></tr><tr valign=top><td align=left>Data </td><td align=left>16K </td><td align=left>512 </td><td align=left>128 </td><td align=left>4 </td><td align=left>32 </td><td align=left>with MCC: Write-through</tr><tr valign=top><td align=left> </td><td align=left> </td><td align=left> </td><td align=left> </td><td align=left> </td><td align=left> </td><td align=left>without MCC: Copy-back with write allocation</tr><tr valign=top><td align=left></tr></tr></table>The cache operations provided are explained in the table below.Operations marked "Hardware" and "Software" are implemented as marked,and are fast and slow, respectively. Operations marked "NOP" return OKwithout doing anyting. Operations with another operation name performthat operation rather than their own. Partial operations marked "Entire"actually perform an "Entire" operation. When the MCC is installed,operations upon the data cache are performed upon both the data cache andthe MCC. Lines "Data-Data" and "Data-MCC" desribe the data cache andMCC, respectively, portions of a data cache operation.<p><table><tr valign=top><th align=left> MCC: </th><th align=left> </th><th align=left> No </th><th align=left> No </th><th align=left> Yes </th><th align=left> Yes </th><th align=left> Yes</tr><tr valign=top><th align=left> Cache Type: </th><th align=left> </th><th align=left> Instr </th><th align=left> Data </th><th align=left> Instr </th><th align=left> Data-Data</th><th align=left> Data-MCC</tr><tr><td colspan="9"><hr></tr><tr valign=top><td align=left></tr><tr valign=top><td align=left><b><i><a href="./cacheLib.html#cacheInvalidate">cacheInvalidate</a></i>( )</b> </td><td align=left>entire </td><td align=left> H/W </td><td align=left> H/W </td><td align=left> H/W </td><td align=left> H/W </td><td align=left> S/W </tr><tr valign=top><td align=left> </td><td align=left> </td><td align=left> </td><td align=left>partial</td><td align=left> Entire </td><td align=left> S/W </td><td align=left> Entire </td><td align=left> S/W </td><td align=left> S/W</tr><tr valign=top><td align=left></tr><tr valign=top><td align=left><b><i><a href="./cacheLib.html#cacheFlush">cacheFlush</a></i>( )</b> </td><td align=left>entire </td><td align=left> NOP </td><td align=left> Clear </td><td align=left> NOP </td><td align=left> NOP </td><td align=left> S/W</tr><tr valign=top><td align=left> </td><td align=left> </td><td align=left> </td><td align=left>partial</td><td align=left> NOP </td><td align=left> Clear </td><td align=left> NOP </td><td align=left> NOP </td><td align=left> Clear</tr><tr valign=top><td align=left></tr><tr valign=top><td align=left><b><i><a href="./cacheLib.html#cacheClear">cacheClear</a></i>( )</b> </td><td align=left>entire </td><td align=left> H/W </td><td align=left> S/W </td><td align=left> H/W </td><td align=left> H/W </td><td align=left> S/W</tr><tr valign=top><td align=left> </td><td align=left> </td><td align=left> </td><td align=left>partial</td><td align=left> Entire </td><td align=left> S/W </td><td align=left> Entire </td><td align=left> S/W </td><td align=left> S/W</tr><tr valign=top><td align=left></tr><tr valign=top><td align=left><b><i><a href="./cacheLib.html#cacheLock">cacheLock</a></i>( )</b> and </td><td align=left>entire </td><td align=left> S/W </td><td align=left> S/W </td><td align=left> S/W </td><td align=left> S/W </td><td align=left> NOP</tr><tr valign=top><td align=left><b><i><a href="./cacheLib.html#cacheUnlock">cacheUnlock</a></i>( )</b> </td><td align=left>partial</td><td align=left> S/W </td><td align=left> S/W </td><td align=left> S/W </td><td align=left> S/W </td><td align=left> NOP</tr><tr valign=top><td align=left></tr></tr></table>The architecture of the optional Multicache Controller (MCC) is explainedin the table below. The MCC supports cache coherency via snooping, anddoes not support line locking.<p>The MCC does not have a <b>CACHE_TYPE</b> value for <b><i><a href="./cacheLib.html#cacheEnable">cacheEnable</a></i>( )</b> or<b><i><a href="./cacheLib.html#cacheDisable">cacheDisable</a></i>( )</b>. For enable and disable operations, the MCC is treated asan extension of both the on-chip data and instruction caches. If eitherthe data or instruction caches are enabled, the MCC is enabled. If boththe data and the instruction caches are disabled, the MCC is disabled.For invalidate, flush, and clear operations the MCC is treated as anextension of only the on-chip data cache. The <b><i><a href="./cacheLib.html#cacheInvalidate">cacheInvalidate</a></i>( )</b>,<b><i><a href="./cacheLib.html#cacheFlush">cacheFlush</a></i>( )</b>, and <b><i><a href="./cacheLib.html#cacheClear">cacheClear</a></i>( )</b> operations for the instruction cacheoperate only on the on-chip instruction cache. However these operationsfor the data cache operate on both the on-chip data cache and the MCC.<p><table><tr valign=top><th align=left> </th><th align=left> </th><th align=left> </th><th align=left> </th><th align=left>Block Size</tr><tr valign=top><th align=left>Cache Type </th><th align=left>Size </th><th align=left>Blocks </th><th align=left>Ways</th><th align=left> (bytes) </th><th align=left> Mode</tr><tr><td colspan="6"><hr></tr><tr valign=top><td align=left></tr><tr valign=top><td align=left>MCC on MBus </td><td align=left> 0, 1M </td><td align=left> 0, 8K </td><td align=left> 1 </td><td align=left> 4*32 </td><td align=left> Copy-back</tr><tr valign=top><td align=left>MCC on XBus </td><td align=left> 512K, 1M, 2M </td><td align=left> 2K, 4K, 8K </td><td align=left> 1 </td><td align=left> 4*64 </td><td align=left> Copy-back</tr><tr valign=top><td align=left></tr></tr></table>Any input peripheral that does not support cache coherency cay be accessedthrough either a cached buffer with a partial <b><i>cacheTiTms390Invalidate</i>( )</b>operation, or an uncached buffer without it. (<b><i><a href="./cacheLib.html#cacheInvalidate">cacheInvalidate</a></i>( )</b> cannotbe used; it is a NOP since it assumes cache coherency.) Choose whicheveris faster for the application.<p>Any output peripheral that does not support cache coherency may beaccessed through either a cached buffer with a partial <b><i>cacheTiTms390Flush</i>( )</b>operation, or an uncached buffer without it. (<b><i><a href="./cacheLib.html#cacheFlush">cacheFlush</a></i>( )</b> cannot beused; it is a NOP since it assumes cache coherency.) Choose whichever isfaster for the application.<p>Any peripheral that supports cache coherency should be accessed through acached buffer without using any of the above operations. Using either anuncached buffer or any of the above operations will just slow the systemdown.<p>MMU (Memory Management Unit) support is needed to mark pages cacheableor non-cacheable. For more information, see the manual entry for vmLib.<p>For general information about caching, see the manual entry for cacheLib.<p></blockquote><h4>INCLUDE FILES</h4><blockquote><p><b>cacheLib.h</b><p></blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheTiTms390Lib.html#top">cacheTiTms390Lib</a></b>, <b><a href="./cacheLib.html#top">cacheLib</a></b>, <b><a href="./vmLib.html#top">vmLib</a></b><hr><a name="cacheTiTms390LibInit"></a><p align=right><a href="rtnIndex.html"><i>Libraries : Routines</i></a></p></blockquote><h1><i>cacheTiTms390LibInit</i>( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong><i>cacheTiTms390LibInit</i>( )</strong> - initialize the TI TMS390 cache library</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>STATUS cacheTiTms390LibInit ( CACHE_MODE instMode, /* instruction cache mode */ CACHE_MODE dataMode /* data cache mode */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine initializes the function pointers for the TI TMS390cache library. The board support package can select this cache library byassigning the function pointer <b>sysCacheLibInit</b> to <b><i><a href="./cacheTiTms390Lib.html#cacheTiTms390LibInit">cacheTiTms390LibInit</a></i>( )</b>.<p>The only available cache mode is <b>CACHE_COPYBACK</b>.<p></blockquote><h4>RETURNS</h4><blockquote><p>OK, or ERROR if cache control is not supported.</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheTiTms390Lib.html#top">cacheTiTms390Lib</a></b><hr><a name="cacheTiTms390VirtToPhys"></a><p align=right><a href="rtnIndex.html"><i>Libraries : Routines</i></a></p></blockquote><h1><i>cacheTiTms390VirtToPhys</i>( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong><i>cacheTiTms390VirtToPhys</i>( )</strong> - translate a virtual address for cacheLib</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void * cacheTiTms390VirtToPhys ( void * address /* virtual address */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine performs a 32-bit virtual to 32-bit physical addresstranslation in the current context.<p></blockquote><h4>RETURNS</h4><blockquote><p>The physical address translation bits [31:0] of a virtualaddress argument, or NULL if the virtual address is not valid, or thephysical address does not fit in 32 bits.<p></blockquote><h4>RETURNS</h4><blockquote><p>N/A</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheTiTms390Lib.html#top">cacheTiTms390Lib</a></b><hr><a name="cacheTiTms390PhysToVirt"></a><p align=right><a href="rtnIndex.html"><i>Libraries : Routines</i></a></p></blockquote><h1><i>cacheTiTms390PhysToVirt</i>( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong><i>cacheTiTms390PhysToVirt</i>( )</strong> - translate a physical address for drivers</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void * cacheTiTms390PhysToVirt ( void * address /* physical address */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine performs a 32-bit physical to 32-bit virtual addresstranslation in the current context.<p>It works for only DRAM addresses of the first EMC.<p>It guesses likely virtual addresses, and checks its guesses with<b>VM_TRANSLATE</b>. A likely virtual address is the same as the physicaladdress, or some multiple of 16M less. If any match, it succeeds. Ifall guesses are wrong, it fails.<p></blockquote><h4>RETURNS</h4><blockquote><p>The virtual address that maps to the physical address bits[31:0] argument, or NULL if it fails.<p></blockquote><h4>RETURNS</h4><blockquote><p>N/A</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheTiTms390Lib.html#top">cacheTiTms390Lib</a></b><hr><a name="cleanUpStoreBuffer"></a><p align=right><a href="rtnIndex.html"><i>Libraries : Routines</i></a></p></blockquote><h1><i>cleanUpStoreBuffer</i>( )</h1> <blockquote></a></blockquote><h4>NAME</h4><blockquote> <p><strong><i>cleanUpStoreBuffer</i>( )</strong> - clean up store buffer after a data store error interrupt</p></blockquote><h4>SYNOPSIS</h4><blockquote><p><pre>void cleanUpStoreBuffer ( UINT mcntl, /* Value of MMU Control Register */ BOOL exception /* TRUE if exception, FALSE if int */ )</pre></blockquote><h4>DESCRIPTION</h4><blockquote><p>This routine cleans up the store buffer after a data store errorinterupt. The first queued store is retried. It is logged as either arecoverable or unrecoverable error. Then the store buffer is re-enabledand other queued stores are processed by the store buffer.<p></blockquote><h4>RETURNS</h4><blockquote><p>N/A</blockquote><h4>SEE ALSO</h4><blockquote><p><b><a href="./cacheTiTms390Lib.html#top">cacheTiTms390Lib</a></b></body></html>⌨️ 快捷键说明
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