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vxworks相关论文

<dd><p class="Body"><a name="85156"> </a>The PentiumPro processor implements the concept of model-specific registers (MSRs) to control hardware functions in the processor or to monitor processor activity. The new registers control the debug extensions, the performance counters, the machine-check exception capability, the machine check architecture, and the MTRRs. The MSRs can be read and written to using the RDMSR and WRMSR instructions, respectively. </p>
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<h4 class="H4"><i><a name="85157">Counters</a></i></h4>
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<h5 class="HU"><i><a name="85158">Performance Monitoring Counters (PMC)</a></i></h5>
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<dd><p class="Body"><a name="85159"> </a>The PentiumPro processor has two performance-monitoring counters for use in monitoring internal hardware operations. These counters are duration or event counters that can be programmed to count any of approximately 100 different types of events, such as the number of instructions decoded, number of interrupts received, or number of cache loads. </p>
<dd><p class="Body"><a name="85160"> </a>PMC is enabled in <b class="routine"><i class="routine">sysHwInit</i></b><b>(&nbsp;)</b>. Selected events in the default configuration are PMC0 = number of hardware interrupts received and PMC1 = number of misaligned data memory references.</p>
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<h5 class="HU"><i><a name="85162">Time Stamp Counter (TSC)</a></i></h5>
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<dd><p class="Body"><a name="85163"> </a>The PentiumPro processor provides a 64-bit time-stamp counter that is incremented every processor clock cycle. The counter is incremented even when the processor is halted by the HLT instruction or the external STPCLK# pin. The time-stamp counter is set to 0 following a hardware reset of the processor. The RDTSC instruction reads the time stamp counter and is guaranteed to return a monotonically increasing unique value whenever executed, except for 64-bit counter wraparound. Intel guarantees, architecturally, that the time-stamp counter frequency and configuration will be such that it will not wraparound within 10 years after being reset to 0. The period for counter wrap is several thousands of years in the PentiumPro and Pentium processors.</p>
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<h4 class="H4"><i><a name="85164">Double-word Integers: <b class="symbol_lc">long long</b> </a></i></h4>
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<dd><p class="Body"><a name="85166"> </a>The double-word integer <b class="symbol_lc">long long</b> is not supported, except as an artifact of your particular architecture and compiler. For more information about handling unsupported features, please see the <i class="title">Customer Support User's Guide</i>.</p>
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<h4 class="H4"><i><a name="85168">Context Switching</a></i></h4>
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<dd><p class="Body"><a name="85169"> </a>Hardware multitasking and the TSS descriptor are not used. VxWorks creates a dummy exception stack frame, loads the registers from the TCB, and then starts the task.</p>
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<h4 class="H4"><i><a name="85171">ISA/EISA Bus</a></i></h4>
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<dd><p class="Body"><a name="85173"> </a>The optional PC-compatible hardware cards supported in this release (the Ethernet adapter cards and the Blunk Microsystems ROM Card) use the ISA/EISA bus architecture.</p>
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<h4 class="H4"><i><a name="85175">PC104 Bus</a></i></h4>
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<dd><p class="Body"><a name="85176"> </a>The PC104 bus is supported and tested with the NE2000-compatible Ethernet card (4i24: Mesa Electronics). Ampro's Ethernet card (Ethernet-II) is also supported.</p>
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<h4 class="H4"><i><a name="85178">PCI Bus</a></i></h4>
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<dd><p class="Body"><a name="85179"> </a>The PCI bus is supported and tested with the Intel EtherExpress PRO100B Ethernet card. Several functions to access PCI configuration space are supported. Functions addressed here include:</p>
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<ul class="Bullet" type="disc"><li><a name="85180"> </a>Locate the device by deviceID and vendorID. </li></ul>
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<ul class="Bullet" type="disc"><li><a name="85181"> </a>Locate the device by classCode. </li></ul>
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<ul class="Bullet" type="disc"><li><a name="85182"> </a>Generate the special cycle. </li></ul>
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<ul class="Bullet" type="disc"><li><a name="85183"> </a>Access its configuration registers. </li></ul>
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<h4 class="H4"><i><a name="85186">Software Floating-Point Emulation</a></i></h4>
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<dd><p class="Body"><a name="85187"> </a>The software floating-point library is supported for the x86 architectures; select <b class="symbol_UC">INCLUDE_SW_FP</b> for inclusion in the project facility VxWorks view to include the library in your system image. This library emulates each floating point instruction, by using the exception "Device Not Available." For other floating-point support information, see <a href="x-ix863.html#84448"><i class="title">Supported Routines in mathALib</i></a>.</p>
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<h4 class="H4"><i><a name="85193">VxWorks Memory Layout</a></i></h4>
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<dd><p class="Body"><a name="85197"> </a>Two memory layouts for the x86 are shown in the following figures: <a href="x-ix864.html#88466">Figure&nbsp;D-2</a> illustrates the typical upper memory configuration, while <a href="x-ix864.html#88405">Figure&nbsp;D-1</a> shows a lower memory option. These figures contain the following labels:<p class="table">

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<p class="BodyLeft"><a name="87196"> </a>Interrupt Vector Table </p>

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<p class="BodyLeft"><a name="87198"> </a>Table of exception/interrupt vectors.</p>

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<p class="BodyLeft"><a name="87200"> </a>GDT </p>

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<p class="BodyLeft"><a name="87202"> </a>Global descriptor table.</p>
<p class="BodyLeft"><a name="87245"> </a>Anchor for the shared memory network (if there is shared memory on the board).</p>

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<p class="BodyLeft"><a name="87208"> </a>Boot Line </p>

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<p class="BodyLeft"><a name="87210"> </a>ASCII string of boot parameters.</p>

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<p class="BodyLeft"><a name="87212"> </a>Exception Message </p>

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<p class="BodyLeft"><a name="87214"> </a>ASCII string of the fatal exception message.</p>

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<p class="BodyLeft"><a name="87216"> </a>FD DMA Area </p>

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<p class="BodyLeft"><a name="87218"> </a>Diskette (floppy device) direct memory access area.</p>

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<p class="BodyLeft"><a name="87220"> </a>Initial Stack </p>

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<p class="BodyLeft"><a name="87222"> </a>Initial stack for <b class="routine"><i class="routine">usrInit</i></b><b>(</b>&nbsp;<b>)</b>, until <b class="routine"><i class="routine">usrRoot</i></b><b>(</b>&nbsp;<b>)</b> gets allocated stack.</p>

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<p class="BodyLeft"><a name="87224"> </a>System Image </p>

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<p class="BodyLeft"><a name="87226"> </a>Entry point for VxWorks.</p>

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<p class="BodyLeft"><a name="87228"> </a>WDB Memory Pool </p>

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<p class="BodyLeft"><a name="87230"> </a>Size depends on the macro <b class="symbol_UC">WDB_POOL_SIZE</b> which defaults to one-sixteenth of the system memory pool. This space is used by the target server to support host-based tools. Modify <b class="symbol_UC">WDB_POOL_SIZE </b>under <b class="symbol_UC">INCLUDE_WDB</b>.</p>

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<p class="BodyLeft"><a name="87232"> </a>Interrupt Stack </p>

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<p class="BodyLeft"><a name="87234"> </a>Size is defined by <b class="symbol_UC">ISR_STACK_SIZE</b> under <b class="symbol_UC">INCLUDE_KERNEL</b>. Location depends on system image size. </p>

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<p class="BodyLeft"><a name="87236"> </a>System Memory Pool </p>

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<p class="BodyLeft"><a name="87238"> </a>Size depends on size of system image and interrupt stack. The end of the free memory pool for this board is returned by <b class="routine"><i class="routine">sysMemTop</i></b><b>(</b>&nbsp;<b>)</b>.</p>

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<dd><p class="Body"><a name="85292"> </a>All addresses shown in <a href="x-ix864.html#88466">Figure&nbsp;D-2</a> are relative to the start of memory for a particular target board. The start of memory (corresponding to 0x0 in the memory-layout diagram) is defined as <b class="symbol_UC">LOCAL_MEM_LOCAL_ADRS</b> under <b class="symbol_UC">INCLUDE_MEMORY_CONFIG</b> for each target.</p>
<dd><p class="Body"><a name="85294"> </a>In general, the boot image is placed in lower memory and the VxWorks image is placed in upper memory, leaving a gap between lower and upper memory. Some BSPs have additional configurations which must fit within their hardware constraints. For details, see the reference entry for each specific BSP. &nbsp;&nbsp;<div class="frame">
<h4 class="EntityTitle"><a name="88405"><font face="Helvetica, sans-serif" size="-1" class="sans">Figure D-1:&nbsp;&nbsp;VxWorks System Memory Layout (x86 Lower Memory) </font></a></h4>

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<div class="Anchor"><a name="88461"> </a><img class="figure" border="0" src="images/x-ix860.gif">
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<h4 class="EntityTitle"><a name="88466"><font face="Helvetica, sans-serif" size="-1" class="sans">Figure D-2:&nbsp;&nbsp;VxWorks System Memory Layout (x86 Upper Memory)</font></a></h4>

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<div class="Anchor"><a name="88527"> </a><img class="figure" border="0" src="images/x-ix86a1.gif">
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