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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN"><html><head><link rel="STYLESHEET" type="text/css" href="wrs.css"><title> ARM </title></head><body bgcolor="FFFFFF"><p class="navbar" align="right"><a href="index.html"><img border="0" alt="[Contents]" src="icons/contents.gif"></a><a href="GuideIX.html"><img border="0" alt="[Index]" src="icons/index.gif"></a><a href="x-arm.html"><img border="0" alt="[Top]" src="icons/top.gif"></a><a href="x-arm3.html"><img border="0" alt="[Prev]" src="icons/prev.gif"></a><a href="x-arm5.html"><img border="0" alt="[Next]" src="icons/next.gif"></a></p><font face="Helvetica, sans-serif" class="sans"><h3 class="H2"><i><a name="84558">G.4 Interface Variations</a></i></h3></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84559"> </a>This section describes particular features and routines that are specific to ARM targets in one of the following ways:</p></dl><dl class="margin"><p class="listspace"><ul class="Bullet" type="disc"><li><a name="84560"> </a>available only on ARM targets</li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="84561"> </a>parameters specific to ARM targets</li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="84562"> </a>special restrictions or characteristics on ARM targets.</li></ul></p></dl><dl class="margin"><dd><p class="Body"><a name="84563"> </a>For more complete documentation on these routines, see the reference entries.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84564">Restrictions on <b class="routine"><i class="routine">cret</i></b><b>( )</b>and <b class="routine"><i class="routine">tt</i></b><b>( )</b></a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84565"> </a>These routines make assumptions about the standard prologue for routines. If routines are written in assembly language, or in another language that generates a different prologue, unexpected results may occur. </p><dd><p class="Body"><a name="84566"> </a><b class="routine"><i class="routine">tt</i></b><b>( )</b> does not report the parameters to C functions as it cannot determine these from the code generated by the compiler.</p></dl></dl><dl class="margin"><dd><p class="table" callout><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td valign="top" width="40"><br><img border="0" alt="*" src="icons/caution.gif"></td><td><hr><div class="CalloutCell"><a name="85000"><b class="symbol_UC"><font face="Helvetica, sans-serif" size="-1" class="sans">CAUTION: </font></b></a>The Thumb kernel is compiled without backtrace structures. This means that <b class="routine"><i class="routine">tt</i></b><b>( )</b> does not work within kernel routines and <b class="routine"><i class="routine">cret</i></b><b>( )</b> occasionally does the wrong thing. Thumb breakpoints and single-stepping work even if the code is compiled without backtrace structures. One solution for debugging is to use ARM state and then switch to Thumb state for your final debugging and production.</div></td></tr><tr valign="top"><td></td><td><hr></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p callout></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="86122"><b class="symbol_lc">cacheLib </b></a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="86126"> </a>The <b class="routine"><i class="routine">cacheLock</i></b><b>( )</b> and <b class="routine"><i class="routine">cacheUnlock</i></b><b>( )</b> routines always return ERROR (see <a href="x-arm5.html#84715"><i class="title">Caches</i></a>). Use of the cache and MMU are very closely linked on ARM processors. Consequently, if <b class="library">cacheLib</b> is used, <b class="library">vmLib</b> is also required. In addition, the <b class="library">cacheLib</b> and <b class="library">vmLib</b> calls need to be coordinated, see <a href="x-arm5.html#84744"><i class="title">Memory Management Unit</i></a>.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84585"><b class="symbol_lc">dbgLib</b> </a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84586"> </a>Many ARM processors have no debug or trace mode and no support for hardware-assisted debugging. Because of this, VxWorks for ARM uses only software breakpoints. When you set a software breakpoint, VxWorks replaces an instruction with a known undefined instruction. VxWorks restores the original code when the breakpoint is removed; if memory is examined or disassembled, the original code is shown.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84587"><b class="symbol_lc">dbgArchLib</b> </a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84588"> </a>If you are using the target shell, note that the following additional architecture-specific routines are available to you: </p></dl></dl><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84589"><b class="routine"><i class="routine">psrShow</i></b><b>( )</b> </a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84590"> </a>Display the symbolic meaning of a specified PSR value on the standard output.</p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84591"><b class="routine"><i class="routine">cpsr</i></b><b>( )</b> </a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84592"> </a>Return the contents of the Current Processor Status Register (CPSR) of the specified task.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84593"><b class="symbol_lc">intALib</b> </a></i></h4></font><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84594"><b class="routine"><i class="routine">intLock</i></b><b>( )</b> and <b class="routine"><i class="routine">intUnlock</i></b><b>( )</b> </a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84595"> </a>The routine <b class="routine"><i class="routine">intLock</i></b><b>( )</b> returns the I bit from the CPSR as the lock-out key for the interrupt level prior to the call to <b class="routine"><i class="routine">intLock</i></b><b>( )</b>. The routine <b class="routine"><i class="routine">intUnlock</i></b><b>( )</b> takes this value as a parameter. For ARM, these routines control the CPU interrupt mask directly. They do not manipulate the interrupt levels in the interrupt controller chip.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84596"><b class="symbol_lc">intArchLib</b> </a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84597"> </a>ARM processors generally have no on-chip interrupt controllers to handle the interrupts multiplexed on the IRQ pin. Control of interrupts is a BSP-specific matter. All of these routines are connected by function pointers to routines which must be provided in ARM BSPs by a standard interrupt controller driver. For general information on interrupt controller drivers, see <i class="title">Wind Technical Note #46</i>. For special requirements or limitations, see the appropriate interrupt controller device driver documents.</p></dl></dl><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84598"><b class="routine"><i class="routine">intLibInit</i></b><b>( )</b> </a></i></h5></font><dl class="margin">⌨️ 快捷键说明
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