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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN"><html><head><link rel="STYLESHEET" type="text/css" href="wrs.css"><title> PowerPC </title></head><body bgcolor="FFFFFF"><p class="navbar" align="right"><a href="index.html"><img border="0" alt="[Contents]" src="icons/contents.gif"></a><a href="GuideIX.html"><img border="0" alt="[Index]" src="icons/index.gif"></a><a href="x-ppc.html"><img border="0" alt="[Top]" src="icons/top.gif"></a><a href="x-ppc3.html"><img border="0" alt="[Prev]" src="icons/prev.gif"></a><a href="x-arm.html"><img border="0" alt="[Next]" src="icons/next.gif"></a></p><font face="Helvetica, sans-serif" class="sans"><h3 class="H2"><i><a name="84607">F.4 Architecture Considerations</a></i></h3></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84608"> </a>This section describes the following characteristics of the PowerPC processors that will affect your VxWorks application:</p></dl><dl class="margin"><ul class="BulletSingle" type="disc"><li><a name="84609"> </a>supervisor/user mode </li></ul><ul class="BulletSingle" type="disc"><li><a name="84610"> </a>24-bit addressing </li></ul><ul class="BulletSingle" type="disc"><li><a name="84611"> </a>byte order </li></ul><ul class="BulletSingle" type="disc"><li><a name="84612"> </a>PowerPC register usage </li></ul><ul class="BulletSingle" type="disc"><li><a name="84613"> </a>caches </li></ul><ul class="BulletSingle" type="disc"><li><a name="84614"> </a>memory management unit (MMU) </li></ul><ul class="BulletSingle" type="disc"><li><a name="84615"> </a>floating-point support </li></ul><ul class="BulletSingle" type="disc"><li><a name="84616"> </a>memory layout </li></ul></dl><dl class="margin"><dd><p class="Body"><a name="84617"> </a>For a more comprehensive documentation of PowerPC architectures, see the appropriate Motorola microprocessor user's manual or the IBM user's manual.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84618">Processor Mode</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84620"> </a>VxWorks always runs in Supervisor mode on processors in the PowerPC family.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84621">24-bit Addressing</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84623"> </a>The PowerPC architecture limits its relative addressing to 24-bit offsets to conform to the EABI (Embedded Application Binary Interface) standard.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84624">Byte Order</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84626"> </a>The byte order used by VxWorks for the PowerPC family is big-endian.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84627">PowerPC Register Usage</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84629"> </a>The PowerPC conventions regarding register usage, stack frame formats, parameter passing between routines, and other factors involving code inter-operability, are defined by the ABI (Application Binary Interface) and the EABI (Embedded Application Binary Interface) protocols. The VxWorks implementation for the PowerPC follows these protocols. <a href="x-ppc4.html#84639">Table F-1</a> shows PowerPC register usage in VxWorks.<p class="table"><h4 class="EntityTitle"><a name="84639"><font face="Helvetica, sans-serif" size="-1" class="sans">Table F-1: PowerPC Registers </font></a></h4><table border="0" cellpadding="0" cellspacing="0"><tr><td colspan="20"><hr class="tablerule"></td></tr><tr valign="middle"><th rowspan="1" colspan="1"><div class="CellHeading"><b><a name="84643"> </a><font face="Helvetica, sans-serif" size="-1" class="sans">Register Name</font></b></div></th><th rowspan="1" colspan="1"><div class="CellHeading"><b><a name="84645"> </a><font face="Helvetica, sans-serif" size="-1" class="sans">Usage</font></b></div></th></tr><tr><td colspan="20"><hr class="tablerule2"></td></tr><tr valign="top"><td colspan=1 rowspan=1><div class="CellBody"><a name="84647"> </a>gpr0 </div></td><td colspan=1 rowspan=1><div class="CellBody"><a name="84649"> </a>Volatile register which may be modified during function linkage. </div></td></tr><tr valign="top"><td colspan=1 rowspan=1><div class="CellBody"><a name="84651"> </a>gpr1 </div></td><td colspan=1 rowspan=1><div class="CellBody"><a name="84653"> </a>Stack frame pointer, always valid. </div></td></tr><tr valign="top"><td colspan=1 rowspan=1><div class="CellBody"><a name="84655"> </a>gpr2 </div></td><td colspan=1 rowspan=1><div class="CellBody"><a name="84657"> </a>Second small data area pointer register (_SDA2_BASE_). </div></td></tr><tr valign="top"><td colspan=1 rowspan=1><div class="CellBody"><a name="84659"> </a>gpr3 -gpr4 </div></td><td colspan=1 rowspan=1><div class="CellBody"><a name="84661"> </a>Volatile registers used for parameter passing and return value. </div></td></tr><tr valign="top"><td colspan=1 rowspan=1><div class="CellBody"><a name="84663"> </a>gpr5-gpr10 </div></td><td colspan=1 rowspan=1><div class="CellBody"><a name="84665"> </a>Volatile registers used for parameter passing. </div></td></tr><tr valign="top"><td colspan=1 rowspan=1><div class="CellBody"><a name="84667"> </a>gpr11-gpr12 </div></td><td colspan=1 rowspan=1><div class="CellBody"><a name="84669"> </a>Volatile registers that may be modified during function linkage. </div></td></tr><tr valign="top"><td colspan=1 rowspan=1><div class="CellBody"><a name="84671"> </a>gpr13 </div></td><td colspan=1 rowspan=1><div class="CellBody"><a name="84673"> </a>Small data area pointer register (_SDA_BASE_). </div></td></tr><tr valign="top"><td colspan=1 rowspan=1><div class="CellBody"><a name="84675"> </a>gpr14-gpr30 </div></td><td colspan=1 rowspan=1><div class="CellBody"><a name="84677"> </a>Non-volatile registers used for local variables. </div></td></tr><tr valign="top"><td colspan=1 rowspan=1><div class="CellBody"><a name="84679"> </a>gpr31 </div></td><td colspan=1 rowspan=1><div class="CellBody"><a name="84681"> </a>Used for local variables or "environment pointers." </div></td></tr><tr valign="top"><td colspan=1 rowspan=1><div class="CellBody"><a name="84683"> </a>fpr0 </div></td><td colspan=1 rowspan=1><div class="CellBody"><a name="84685"> </a>Volatile floating-point register. </div></td></tr><tr valign="top"><td colspan=1 rowspan=1><div class="CellBody"><a name="84687"> </a>fpr1 </div></td><td colspan=1 rowspan=1><div class="CellBody"><a name="84689"> </a>Volatile floating-point register used for parameter passing and return value. </div></td></tr><tr valign="top"><td colspan=1 rowspan=1><div class="CellBody"><a name="84691"> </a>fpr2-fpr8 </div></td><td colspan=1 rowspan=1><div class="CellBody"><a name="84693"> </a>Volatile floating-point registers used for parameter passing. </div></td></tr><tr valign="top"><td colspan=1 rowspan=1><div class="CellBody"><a name="84695"> </a>fpr9-fpr13 </div></td><td colspan=1 rowspan=1><div class="CellBody"><a name="84697"> </a>Volatile floating-point registers. </div></td></tr><tr valign="top"><td colspan=1 rowspan=1><div class="CellBody"><a name="84699"> </a>fpr14-fpr31 </div></td><td colspan=1 rowspan=1><div class="CellBody"><a name="84702"> </a>Non-volatile floating-point registers used for local variables. </div></td></tr><tr><td colspan="20"><hr class="tablerule"></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p></p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84704">Caches</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84708"> </a>The following subsections augment the information in <a href="c-iosys.html#83549"><i class="title">3. I/O System</i></a>.</p><dd><p class="Body"><a name="84709"> </a>PowerPC processors contain an instruction cache and a data cache. In the default configuration, VxWorks enables both caches. To disable the instruction cache, highlight the <b class="symbol_UC">USER_I_CACHE_ENABLE</b> macro in the <b class="guiLabel"><font face="Helvetica, sans-serif" size="-1" class="sans">Params</font></b> tab under <b class="symbol_UC">INCLUDE_CACHE_ENABLE</b> and remove the <b class="symbol_UC">TRUE</b>; to disable the data cache, highlight the <b class="symbol_UC">USER_D_CACHE_ENABLE </b>macro and remove the <b class="symbol_UC">TRUE</b>.</p><dd><p class="Body"><a name="84712"> </a>For most boards, the cache capabilities must be used with the MMU to resolve cache coherency problems. The page descriptor for each page selects the cache mode. This page descriptor is configured by filling the data structure <b class="keyword">sysPhysMemDesc[] </b>defined in <b class="library">sysLib.c</b>. (For more information about cache coherency, see the reference entry for <b class="library">cacheLib</b>. For information about the MMU and VxWorks virtual memory, see <a href="c-vm.html#84369"><i class="title">7. Virtual Memory Interface</i></a>. For MMU information specific to the PowerPC family, see <a href="x-ppc4.html#86306"><i class="title">Memory Management Unit</i></a>.)</p><dd><p class="Body"><a name="86293"> </a>The state of both data and instruction caches is controlled by the WIMG<sup><a href="#foot"><b class="FootnoteMarker">1</b></a></sup> information saved either in the BAT (Block Address Translation) registers or in the segment descriptors. Since a default cache state cannot be supplied, each cache may be enabled separately after the corresponding MMU is turned on. For more information on these cache control bits, refer to <i class="title">PowerPC Microprocessor Family: The Programming Environments</i>, published jointly by Motorola and IBM.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="86306">Memory Management Unit</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84740"> </a>The PowerPC MMU architecture required some extensions to the standard VxWorks MMU interface. See <a href="x-ppc3.html#84487"><i class="title">Memory Management Unit</i></a>.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84746">Floating-Point Support</a></i></h4></font><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84747">PowerPC 403 and 860</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84748"> </a>The PowerPC 403 and 860 do not support hardware floating-point instructions. However, VxWorks provides a floating-point library that emulates these mathematical functions. All ANSI floating-point functions have been optimized using libraries from U. S. Software.<p class="table"><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85816"> </a><b class="routine"><i class="routine">acos</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85818"> </a><b class="routine"><i class="routine">asin</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85820"> </a><b class="routine"><i class="routine">atan</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85822"> </a><b class="routine"><i class="routine">atan2</i></b><b>( )</b> </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85824"> </a><b class="routine"><i class="routine">ciel</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85826"> </a><b class="routine"><i class="routine">cos</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85828"> </a><b class="routine"><i class="routine">cosh</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85830"> </a><b class="routine"><i class="routine">exp</i></b><b>( )</b> </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85877"> </a><b class="routine"><i class="routine">fabs</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85879"> </a><b class="routine"><i class="routine">floor</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85881"> </a><b class="routine"><i class="routine">fmod</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85883"> </a><b class="routine"><i class="routine">log</i></b><b>( )</b> </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85885"> </a><b class="routine"><i class="routine">log10</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85917"> </a><b class="routine"><i class="routine">pow</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85919"> </a><b class="routine"><i class="routine">sin</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85891"> </a><b class="routine"><i class="routine">sinh</i></b><b>( )</b> </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85832"> </a><b class="routine"><i class="routine">sqrt</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85834"> </a><b class="routine"><i class="routine">tan</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85836"> </a><b class="routine"><i class="routine">tanh</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85838"> </a></p></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p></p><dd><p class="Body"><a name="85846"> </a>In addition, the following single-precision functions are also available: <p class="table"><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85975"> </a><b class="routine"><i class="routine">acosf</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85977"> </a><b class="routine"><i class="routine">asinf</i></b><b>( )</b> </p>⌨️ 快捷键说明
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