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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN"><html><head><link rel="STYLESHEET" type="text/css" href="wrs.css"><title> ARM </title></head><body bgcolor="FFFFFF"><p class="navbar" align="right"><a href="index.html"><img border="0" alt="[Contents]" src="icons/contents.gif"></a><a href="GuideIX.html"><img border="0" alt="[Index]" src="icons/index.gif"></a><a href="x-arm.html"><img border="0" alt="[Top]" src="icons/top.gif"></a><a href="x-arm4.html"><img border="0" alt="[Prev]" src="icons/prev.gif"></a><a href="x-vxsim.html"><img border="0" alt="[Next]" src="icons/next.gif"></a></p><font face="Helvetica, sans-serif" class="sans"><h3 class="H2"><i><a name="84643">G.5 Architecture Considerations</a></i></h3></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84644"> </a>This section describes the following characteristics of the ARM processors that you may need to keep in mind as you write a VxWorks application:</p></dl><dl class="margin"><ul class="BulletSingle" type="disc"><li><a name="84645"> </a>processor mode and byte order</li></ul><ul class="BulletSingle" type="disc"><li><a name="84646"> </a>ARM/Thumb state </li></ul><ul class="BulletSingle" type="disc"><li><a name="84647"> </a>interrupts and exceptions </li></ul><ul class="BulletSingle" type="disc"><li><a name="84648"> </a>floating point support </li></ul><ul class="BulletSingle" type="disc"><li><a name="84649"> </a>caches </li></ul><ul class="BulletSingle" type="disc"><li><a name="84650"> </a>memory management unit </li></ul><ul class="BulletSingle" type="disc"><li><a name="84651"> </a>WindView </li></ul><ul class="BulletSingle" type="disc"><li><a name="84652"> </a>memory layout</li></ul></dl><dl class="margin"><dd><p class="Body"><a name="84653"> </a>For comprehensive documentation of the ARM architecture and for specific processors, you may wish to refer to the <i class="title">ARM Architecture Reference Manual</i> and the appropriate data sheets of the processors.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84655">Processor Mode and Byte Order</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84656"> </a>VxWorks for ARM executes mainly in 32-bit supervisor mode (SVC32). When exceptions occur which cause the CPU to enter other modes, the kernel generally switches to SVC32 mode for most of the processing. No code should execute in user mode. No support is included for the 26-bit modes, which are obsolete.</p><dd><p class="Body"><a name="84657"> </a>ARM CPUs include some support for both little-endian and big-endian byte orders. This release includes only support for little-endian byte order, but network applications must convert some data to a standard network order, which is big-endian. In particular, in network applications, be sure to convert the port number to network byte order using <b class="routine"><i class="routine">htons</i></b><b>( )</b>.</p><dd><p class="Body"><a name="84658"> </a>For more information about macros and routines to convert byte order from little-endian to big-endian or vice-versa, see the <i class="title">VxWorks Network Programmer's Guide: TCP/IP Under VxWorks</i>.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84659">ARM/Thumb State</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84660"> </a>This release of Tornado for ARM supports both 32-bit instructions (ARM state) and 16-bit instructions (Thumb state). </p></dl></dl><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84661">Thumb Limitation</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84662"> </a>When running a Thumb kernel and using either the host or target shell, passing a function name as a parameter to a function does not pass an address suitable for calling. The failure is due to the fact that addresses in Thumb state must have bit zero set, but the symbol table has bit zero clear. </p><dd><p class="Body"><a name="84663"> </a>Example: At the shell prompt, type the following:</p><dl class="margin"><dd><pre class="Code2"><b><a name="84664">-> sp func1,func2</a></b></pre></dl><dd><p class="Body"><a name="84665"> </a>where <b class="symbol_lc">func1</b> and <b class="symbol_lc">func2</b> are names of functions. Function <b class="symbol_lc">func1</b> is spawned as a task and passed the address of <b class="symbol_lc">func2</b> as a parameter. Unfortunately, that address is not suitable for use as a Thumb function pointer by <b class="symbol_lc">func1</b> because, when the shell looks up <b class="symbol_lc">func2</b> in the symbol table, it gets back an address with bit zero clear. Calling that address causes it to be entered in ARM state, not Thumb state.</p><dd><p class="Body"><a name="84666"> </a>The simplest workaround is to type the following: </p><dl class="margin"><dd><pre class="Code2"><b><a name="84667">-> sp func1,func2 | 1</a></b></pre></dl><dd><p class="Body"><a name="84668"> </a>An alternative is to write <b class="symbol_lc">func1</b> as follows:</p><dl class="margin"><dd><pre class="Code2"><b><a name="84669">extern int func2(void); int func1(void) { return func2(); }</a></b></pre></dl><dd><p class="Body"><a name="84670"> </a>In this case, the loader provides the correct address for <b class="symbol_lc">func2</b> when the object file is loaded. Thus <b class="symbol_lc">func2</b> is entered in Thumb state as required when you type the following:</p><dl class="margin"><dd><pre class="Code2"><b><a name="84671">-> sp func1</a></b></pre></dl><dd><p class="Body"><a name="84672"> </a>A more flexible alternative is to write <b class="symbol_lc">func1</b> as follows:</p><dl class="margin"><dd><pre class="Code2"><b><a name="84673">int func1(FUNCPTR f) { f = (FUNCPTR)((UINT32)f | 1); return f(); }</a></b></pre></dl><dd><p class="Body"><a name="84674"> </a>This allows you to call the function successfully as follows:</p><dl class="margin"><dd><pre class="Code2"><b><a name="84675">-> sp func1,func2</a></b></pre></dl></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84676">Interrupts and Exceptions</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84677"> </a>When an ARM interrupt or exception occurs, the CPU switches to one of several exception modes, each of which has a number of dedicated registers. In order to make the handlers reentrant, the stub routines that VxWorks installs to trap interrupts and exceptions switch from the exception mode to SVC mode for further processing; the handler cannot be reentrant while executing in an exception mode because reentry would destroy the link register. When an exception or base-level interrupt handler is installed by a call to VxWorks, the address of the handler is stored for use by the stub when the mode switching is complete. The handler returns to the stub routine to restore the processor state to what it was before the exception occurred. Exception handlers (excluding interrupt handlers) can modify the state to be restored by changing the contents of the register set passed to the handler.</p><dd><p class="Body"><a name="84678"> </a>ARM processors do not, in general, have on-chip interrupt controllers. All interrupts are multiplexed on the IRQ pin except for FIQs (see <a href="x-arm5.html#84699"><i class="title">Fast Interrupt (FIQ)</i></a>). Therefore routines must be provided within the BSP to enable and disable specific device interrupts, to install handlers for specific device interrupts, and to determine the cause of the interrupt and dispatch the correct handler when an interrupt occurs. These routines are installed by setting function pointers. For examples, see the interrupt control modules in <i class="textVariable">installDir</i><b class="file">/target/src/drv/intrCtl</b>. A device driver then installs an interrupt handler by calling <b class="routine"><i class="routine">intConnect</i></b><b>( )</b>. For more information, see <i class="title">Wind Technical Note #46</i>.</p><dd><p class="Body"><a name="84682"> </a>Exceptions other than interrupts are handled in a similar fashion: the exception stub switches to SVC mode and then calls any installed handler. Handlers are installed by calls to <b class="routine"><i class="routine">excVecSet</i></b><b>( )</b> and the addresses of installed handlers can be read by calls to <b class="routine"><i class="routine">excVecGet</i></b><b>( )</b>.</p></dl></dl><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84683">Thumb State Interrupt Handling</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84684"> </a>When an interrupt occurs in a Thumb kernel (in other words, a kernel built with <b class="symbol_UC">CPU=ARM7TDMI_T</b>) the CPU switches to ARM state. The kernel code then saves appropriate state information and calls the interrupt demultiplexing code. This code can, in theory, be ARM or Thumb code but only Thumb code is supported and tested.</p><dd><p class="Body"><a name="84685"> </a>The interrupt demultiplexing code then calls the device-specific ISR (the routine installed by a call to <b class="routine"><i class="routine">intConnect</i></b><b>( )</b>). Again, in theory, that code could be ARM or Thumb code but only Thumb code is supported and tested.</p></dl></dl><dl class="margin"><dd><p class="table" callout><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td valign="top" width="40"><br><img border="0" alt="*" src="icons/caution.gif"></td><td><hr><div class="CalloutCell"><a name="84690"><b class="symbol_UC"><font face="Helvetica, sans-serif" size="-1" class="sans">CAUTION: </font></b></a>In non-Thumb kernels (kernels built with <b class="symbol_UC">CPU=ARM7TDMI</b> rather than <b class="symbol_UC">CPU=ARM7TDMI_T</b>) only ARM code ISRs will be entered correctly. </div></td></tr><tr valign="top"><td></td><td><hr></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p callout></dl><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84696">Interrupt stacks</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84697"> </a>VxWorks for ARM uses a separate interrupt stack to avoid having to make task interrupt stacks big enough to accommodate the needs of interrupt handlers. The ARM architecture has a dedicated stack pointer for its IRQ interrupt mode. However, because the low-level interrupt handling code must be reentrant, IRQ mode is only used on entry and exit from the handler; an interrupt destroys the IRQ mode link register. The majority of interrupt handling code runs in SVC mode on a dedicated SVC-mode interrupt stack.</p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84699">Fast Interrupt (FIQ)</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84700"> </a>Fast Interrupt (FIQ) is not handled by VxWorks. BSPs can use FIQ as they wish, but VxWorks code should not be called from FIQ handlers. If this functionality is required, the preferred mechanism is to downgrade the FIQ to an IRQ by software access to appropriately-designed hardware which generates an IRQ. The IRQ handler can then make the call to VxWorks.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84701">Floating-Point Support</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84702"> </a>In this release, no support is included for floating-point coprocessors. Support for floating-point arithmetic is provided as part of the GNU ARM distribution from the Free Software Foundation, in <b class="library">libgcc.a</b>. The GNU implementation utilizes call-outs rather than emulation of floating-point instructions.</p></dl></dl><dl class="margin"><dd><p class="table" callout><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td valign="top" width="40"><br><img border="0" alt="*" src="icons/warning.gif"></td><td><hr><div class="CalloutCell"><a name="84707"><b class="symbol_UC"><font face="Helvetica, sans-serif" size="-1" class="sans">WARNING: </font></b></a>On ARM processors, <b class="symbol_lc">double</b> variables have a different format from IEEE double on most other processors. The bit pattern used by the ARM hardware and software floating point implementations follows the IEEE standard; however, the byte order is different from standard practice leading to a <i class="term">cross-endian</i> implementation. Be careful when sharing <b class="symbol_lc">double</b> values in memory between ARM and other processors.</div></td>⌨️ 快捷键说明
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