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<dd><p class="Body"><a name="84845"> </a>All floating-point exceptions (if enabled) result in the suspension of the offending task and a message sent through the exception handling task, <b class="routine"><i class="routine">excTask</i></b><b>(</b>&nbsp;<b>)</b>. The floating-point unit is flushed so that other tasks can still use the hardware and continue their numeric processing.</p>
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<b class="HU-bullet"><li><a name="84847"> </a><font face="Helvetica, sans-serif" size="-1" class="sans">Deferred Exceptions </font></li></b>
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<dd><p class="Body"><a name="84848"> </a>Floating-point exceptions on the SPARC floating-point units are deferred. When they occur in the FPU, they do not immediately interrupt the CPU (integer unit). Instead they remain pended until they are pushed out of the queue by additional floating-point operations or an FSR access. </p>
<dd><p class="Body"><a name="84849"> </a>If one of the last floating-point operations causes an unmasked exception before a context switch, saving the task's context flushes out the exception while in the kernel. The exception handler checks for this special case and works its way back to the kernel so that it can continue the context switch. When the task that caused the exception is switched back in, it continues in the exception handler and suspends itself. The relationship between a deferred exception and a context switch cannot be controlled due to its asynchronous nature.</p>
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<b class="HU-bullet"><li><a name="84850"> </a><font face="Helvetica, sans-serif" size="-1" class="sans">Floating-Point Exception Simulation</font></li></b>
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<dd><p class="Body"><a name="84852"> </a>SPARCmon is a product from Sun Microsystems that you can attach to the floating-point exception vectors to handle all exception cases for the SPARC. Any floating-point exceptions must be simulated by software and the queue flushed of all pending operations. This simulation fixes the error that caused the exception whenever possible, or takes some default action (for example, suspends the task).</p>
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<h4 class="H4"><i><a name="84854">Stack Pointer Usage</a></i></h4>
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<dd><p class="Body"><a name="84856"> </a>Because the stack pointer can advance without stack memory actually being written or read, it is possible for the stack high water marker to appear below the current stack pointer. In other words, current stack usage can be greater than the high stack usage. This is an artifact of the SPARC architecture's rolling register windows.</p>
<dd><p class="Body"><a name="84857"> </a>The stack pointer is used very little. The local and output registers in each register window perform the bulk of stack operations. The stack is used for long argument lists, or if a window overflow exception pushes registers onto the stack.</p>
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<h4 class="H4"><i><a name="84860">SPARClite Overview</a></i></h4>
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<dd><p class="Body"><a name="84861"> </a>All information pertaining to the SPARC applies to the SPARClite, with the addition of the architectural enhancements described in the following subsections.</p>
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<h5 class="HU"><i><a name="84864">Instruction and Data Cache Locking</a></i></h5>
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<dd><p class="Body"><a name="84865"> </a>The SPARClite allows the global and local locking of the instruction and data caches. The ability to lock instructions and/or data in the caches allows for higher performance and more deterministic systems. The locking must be done in such a way that overall system performance is improved, not degraded. For a better real-time system, call <b class="routine"><i class="routine">cacheMb930LockAuto</i></b><b>(</b>&nbsp;<b>) </b>to enable instruction and data cache locking. After the caches are locked, they cannot be unlocked or disabled.</p>
<dd><p class="Body"><a name="84867"> </a>To enhance performance, some of the VxWorks kernel data items are locked in the data cache. This uses approximately 128 bytes. The remainder of the data cache is available to the developer. Additional data can be locked in the cache using the BSP.</p>
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<dd><font face="Helvetica, sans-serif" size="-1" class="sans">
<h5 class="HU"><i><a name="84870">USS Floating-Point Emulation Library</a></i></h5>
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<dd><p class="Body"><a name="84871"> </a>The SPARClite does not have a floating-point coprocessor; thus, the USS floating-point emulation library is used. Using the <b class="command">-msparclite</b> compile flag allows this library to be accessed by your code for floating-point calculations.</p>
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<h4 class="H4"><i><a name="84875">Memory Layout</a></i></h4>
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<dd><p class="Body"><a name="84876"> </a>The memory layout of both the SPARC and SPARClite processors is shown in <a href="x-sparc4.html#85474">Figure&nbsp;B-1</a>. The memory layout of the microSPARC processor is in <a href="x-sparc4.html#84976">Figure&nbsp;B-2</a>. These figures contain the following labels:<p class="table">

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<p class="BodyLeft"><a name="85543"> </a>SM Anchor </p>

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<p class="BodyLeft"><a name="85545"> </a>Anchor for the shared memory network (if there is shared memory on the board).</p>

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<p class="BodyLeft"><a name="85547"> </a>Boot Line </p>

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<p class="BodyLeft"><a name="85549"> </a>ASCII string of boot parameters.</p>

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<p class="BodyLeft"><a name="85551"> </a>Exception Message </p>

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<p class="BodyLeft"><a name="85553"> </a>ASCII string of the fatal exception message.</p>

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<p class="BodyLeft"><a name="85555"> </a>Interrupt Vector Table </p>

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<p class="BodyLeft"><a name="85557"> </a>Table of exception/interrupt vectors.</p>

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<p class="BodyLeft"><a name="85559"> </a>Initial Stack </p>

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<p class="BodyLeft"><a name="85561"> </a>Initial stack for <b class="routine"><i class="routine">usrInit</i></b><b>(</b>&nbsp;<b>)</b>, until <b class="routine"><i class="routine">usrRoot</i></b><b>(</b>&nbsp;<b>)</b> gets allocated stack.</p>

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<p class="BodyLeft"><a name="85563"> </a>System Image </p>

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<p class="BodyLeft"><a name="85565"> </a>Entry point for VxWorks.</p>

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<p class="BodyLeft"><a name="85567"> </a>WDB Memory Pool </p>

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<p class="BodyLeft"><a name="85569"> </a>Size depends on the macro <b class="symbol_UC">WDB_POOL_SIZE</b> which defaults to one-sixteenth of the system memory pool. This space is used by the target server to support host-based tools. Modify <b class="symbol_UC">WDB_POOL_SIZE</b> under <b class="symbol_UC">INCLUDE_WDB</b>.</p>

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<p class="BodyLeft"><a name="85571"> </a>Interrupt Stack </p>

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<p class="BodyLeft"><a name="85573"> </a>Size is defined by <b class="symbol_UC">ISR_STACK_SIZE</b> under <b class="symbol_UC">INCLUDE_KERNEL</b>. Location depends on system image size. </p>

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<p class="BodyLeft"><a name="85575"> </a>System Memory Pool </p>

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<p class="BodyLeft"><a name="85577"> </a>Size depends on size of system image and interrupt stack. The end of the free memory pool for this board is returned by <b class="routine"><i class="routine">sysMemTop</i></b><b>(</b>&nbsp;<b>)</b>.</p>

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<dd><p class="Body"><a name="84969"> </a>All addresses shown are relative to the start of memory for a particular target board. The start of memory (corresponding to 0x0 in the memory-layout diagram) is defined as <b class="symbol_UC">LOCAL_MEM_LOCAL_ADRS</b> under <b class="symbol_UC">INCLUDE_MEMORY_CONFIG</b> for each target. <div class="frame">
<h4 class="EntityTitle"><a name="85474"><font face="Helvetica, sans-serif" size="-1" class="sans">Figure B-1:&nbsp;&nbsp;VxWorks System Memory Layout (SPARC/SPARClite) </font></a></h4>

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<div class="Anchor"><a name="85537"> </a><img class="figure" border="0" src="images/x-sparc0.gif">
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&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <div class="frame">
<h4 class="EntityTitle"><a name="84976"><font face="Helvetica, sans-serif" size="-1" class="sans">Figure B-2:&nbsp;&nbsp;VxWorks System Memory Layout (microSPARC I &amp; II) </font></a></h4>

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<div class="Anchor"><a name="85055"> </a><img class="figure" border="0" src="images/x-sparca1.gif">
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