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vxworks相关论文

<tr valign=top>
<td align=left>vxWorks </td><td align=left> standard "Tornado-style" vxworks</tr>
<tr valign=top>
<td align=left>vxWorks.st </td><td align=left>  Fully linked stand alone vxWorks including target based shell, symbol table, and network  interface. The network interface is not initialized. There is no WDB agent. </tr>
<tr valign=top>
<td align=left>vxWorks.res_rom </td><td align=left>  Standalone VxWorks image that can be put in ROM. Only the data segment of this ROM image is copied into RAM. </tr>
<tr valign=top>
<td align=left>vxWorks.res_rom_nosym </td><td align=left>  Standalone VxWorks image that can be put in ROM. Only the data segment of this ROM image is copied into RAM. There is no symbol table.  </tr>
<tr valign=top>
<td align=left></tr>
<tr><td colspan="3"><hr></tr>
</tr>

</table>

</blockQuote><h4>Special Routines</h4><blockQuote>
The following routines are specific to this BSP and are available
to the user. The are written in assembly code in <b>sysALib.s</b>. For 
further details see the man pages:
<table>
<tr valign=top>
<td align=left><b><i><a href="../evb403/sysLib.html#sysInByte" >sysInByte</a></i>(&nbsp;)</b> </td><td align=left> input one byte from I/O space</tr>
<tr valign=top>
<td align=left><b><i>sysInWord</i>(&nbsp;)</b> </td><td align=left> input one word from I/O space</tr>
<tr valign=top>
<td align=left><b><i>sysInLong</i>(&nbsp;)</b> </td><td align=left> input one long-word from I/O space</tr>
<tr valign=top>
<td align=left><b><i><a href="../evb403/sysLib.html#sysOutByte" >sysOutByte</a></i>(&nbsp;)</b> </td><td align=left> output one byte to I/O space</tr>
<tr valign=top>
<td align=left><b><i>sysOutWord</i>(&nbsp;)</b> </td><td align=left> output one word to I/O space</tr>
<tr valign=top>
<td align=left><b><i>sysOutLong</i>(&nbsp;)</b> </td><td align=left> output one long-word to I/O space</tr>
<tr valign=top>
<td align=left><b><i><a href="../mbx860/sysLib.html#sysInWordString" >sysInWordString</a></i>(&nbsp;)</b> </td><td align=left> input word string from I/O space</tr>
<tr valign=top>
<td align=left><b><i><a href="../mbx860/sysLib.html#sysInLongString" >sysInLongString</a></i>(&nbsp;)</b> </td><td align=left> input long string from I/O space</tr>
<tr valign=top>
<td align=left><b><i><a href="../mbx860/sysLib.html#sysOutWordString" >sysOutWordString</a></i>(&nbsp;)</b> </td><td align=left> output word string to I/O space</tr>
<tr valign=top>
<td align=left><b><i><a href="../mbx860/sysLib.html#sysOutLongString" >sysOutLongString</a></i>(&nbsp;)</b> </td><td align=left> output long string to I/O space</tr>
<tr valign=top>
<td align=left></tr>
</tr>

</table>

</blockQuote><h4>Known Problems</h4><blockQuote>
bootrom_high (high memory compressed bootrom) 
may fail to boot; psychadelic video suggest video memory
or controller corrupted
<p>
vxWorks_rom_low (low memory uncompressed bootable vxWorks)
feiattach may fail: feiattach might not be
able to obtain enough memory
<p>
Failures during Validation Test Suite (VTS):
<p>
NVRAM test: fails as this BSP has no NVRAM.
<p>
Catastrophic error test: fails as the VTS expects
an exception message but this BSP displays none;
however, the BSP correctly recovers
by rebooting the target.
<p>
Bootline Test :
Bus error test for local error address fails.
Bus error test for off-board error address fails.
Boot commands test failed as the VTS incorrectly presumes a big
endian architecture.
<p>
</blockQuote><h4>Other</h4><blockQuote>
The valid auxiliary clock rates are between 2 ticks per 
second and 2 to the power of 13 ticks per second (2^13 = 8192).
<p>
Warm booting (reboot) is dependent upon the following parameters (shown with
default values) in <b>config.h</b>:
<p>
<pre>#define SYS_WARM_BIOS       0   /* warm start from BIOS */
#define SYS_WARM_FD         1   /* warm start from FD */
#define SYS_WARM_ATA        2   /* warm start from ATA */
#define SYS_WARM_TFFS       3   /* warm start from DiskOnChip */

#define SYS_WARM_TYPE       SYS_WARM_FD /* warm start device */
#define SYS_WARM_FD_DRIVE   0   /* 0 = drive a:, 1 = b: */
#define SYS_WARM_FD_TYPE    0   /* 0 = 3.5" 2HD, 1 = 5.25" 2HD */
#define SYS_WARM_ATA_CTRL   0   /* controller 0 */
#define SYS_WARM_ATA_DRIVE  0   /* 0 = c:, 1 = d: */
</pre>

If SCSI configuration fails, it may be the result of improper SCSI bus 
termination. Check termination carefully on all devices, including
the controller. Note that some devices
have built in termination that is configured via a jumper.
<p>
In order to dynamically update the MMU table entries,
prior to MMU initialization,
several dummy entries
have been added to the end of the memory description
table sysPhysMemDesc. This allows PCI device configuration space,
configured by the BIOS, to be properly mapped into the VxWorks memory
map. This is done by <b><i><a href="./sysLib.html#sysMmuMapAdd">sysMmuMapAdd</a></i>(&nbsp;)</b> in <b>sysLib.c</b>.
<p>
This BSP does not support ISA PnP. Such devices can be supported if
PnP is disabled and the device parameters (IO address, Memory address,
IRQ, DMA channel etc) is set to match its BSP driver configuration. If
the device uses soft-configuration instead of jumpers, an appropriate
utility program, usually available from the device manufacturer,
should be used to setup the device parameters.
<p>
</blockQuote><h4>Pentium and PentiumPro support</h4><blockQuote>
Following features are supported for Pentium and PentiumPro, and they
are enabled in <b><i><a href="./sysLib.html#sysHwInit">sysHwInit</a></i>(&nbsp;)</b>.  See <b><a href="../../ref/pentiumLib.html#top" >pentiumLib</a></b> for more details of these
features.
<p>
<dl>
<dt>
Memory Type Range Registers (MTRRs)
<dd>

If <b>INCLUDE_MTRR_GET</b> is defined, contents of the MTRRS are copied to the 
sysMtrr[] table.  Otherwise it sets the contents of sysMtrr[] to the MTRRs.
<p>

<dt>
Performance Monitoring Counter (PMC)
<dd>

This is an optional feature configured by <b>INCLUDE_PMC</b> macro.
<p>

<dt>
Machine Check Architecture (MCA)
<dd>

<p>

<dt>
Time Stamp Counter (TSC)
<dd>

If <b>INCLUDE_TIMESTAMP_TSC</b> is defined, on-chip TSC is used for the 
time stamp driver.  <b>PENTIUM_TSC_FREQ</b> specifies its frequency.
If it is difined to zero, the frequency is automatically detected.
<p>

<dt>
Enhanced MMU
<dd>

The enhanced MMU is included by defining <b>INCLUDE_MMU_PENTIUMPRO</b> macro.
4KB-page and 4MB-page are supported and configurable by <b>VM_PAGE_SIZE</b>
macro.  Two new memory attribute macros, <b>VM_STATE_WBACK</b> and 
<b>VM_STATE_GLOBAL</b>, are added.  
<b>VM_STATE_WBACK</b> (clear PWT bit) and <b>VM_STATE_WBACK_NOT</b> (set PWT bit)
represents the cache mode of a page.
<b>VM_STATE_GLOBAL</b> (set GLOBAL bit) and <b>VM_STATE_GLOBAL_NOT</b> (clear
GLOBAL bit) represents the global characteristics of a page.
<p>

<dt>
Advanced Programmable Interrupt Controller (APIC)
<dd>

PentiumPro's APIC is supported in either Virtual Wire Mode (define
<b>VIRTUAL_WIRE_MODE</b> in <b>config.h</b>) or Symmetric IO Mode (define 
<b>SYMMETRIC_IO_MODE</b> in <b>config.h</b>).  If neither of them is defined,
VxWorks uses a mode that is set up by BIOS, which could be Virtual
Wire Mode or PIC Mode.  Only Local APIC is used in Virtual Wire Mode,
both Local APIC and IO APIC are used in Symmetric IO Mode.
<p>

<dt>
Data Cache Mode
<dd>

<b>CACHE_COPYBACK</b> data cache mode is default for Pentium. 
It uses Write Back data cache mode with the generic MMU library
for X86 architecture.
<b>CACHE_COPYBACK</b> and <b>CACHE_SNOOP_ENABLE</b> is deafult for PentiumPro.
<b>CACHE_COPYBACK</b> has no effect to the PentiumPro's MMU library
that support page basis Write Back/Write Through cache mode.
<b>CACHE_SNOOP_ENABLE</b> respects MESI cache protocol and doesn't invoke
the WBINVD (write back and invalidate cache) instruction in the
flush routine in the cache library.
<p>
</dl>

</blockQuote><h4>MTRR</h4><blockQuote>
This table shows effective memory type depending on MTRR, PCD, and
PWT setting.
<p>
<table>
<tr valign=top>
<th align=left>MTRR mem type </th><th align=left> PCD value </th><th align=left> PWT value </th><th align=left> Effective mem type</tr>
<tr><td colspan="4"><hr></tr>
<tr valign=top>
<td align=left>UC </td><td align=left> X </td><td align=left> X </td><td align=left> UC</tr>
<tr valign=top>
<td align=left>WC </td><td align=left> 0 </td><td align=left> 0 </td><td align=left> WC</tr>
<tr valign=top>
<td align=left> </td><td align=left> 0 </td><td align=left> 1 </td><td align=left> WC</tr>
<tr valign=top>
<td align=left> </td><td align=left> 1 </td><td align=left> 0 </td><td align=left> WC</tr>
<tr valign=top>
<td align=left> </td><td align=left> 1 </td><td align=left> 1 </td><td align=left> UC</tr>
<tr valign=top>
<td align=left>WT </td><td align=left> 0 </td><td align=left> X </td><td align=left> WT</tr>
<tr valign=top>
<td align=left> </td><td align=left> 1 </td><td align=left> X </td><td align=left> UC</tr>
<tr valign=top>
<td align=left>WP </td><td align=left> 0 </td><td align=left> 0 </td><td align=left> WP</tr>
<tr valign=top>
<td align=left> </td><td align=left> 0 </td><td align=left> 1 </td><td align=left> WP</tr>
<tr valign=top>
<td align=left> </td><td align=left> 1 </td><td align=left> 0 </td><td align=left> UC</tr>
<tr valign=top>
<td align=left> </td><td align=left> 1 </td><td align=left> 1 </td><td align=left> UC</tr>
<tr valign=top>
<td align=left>WB </td><td align=left> 0 </td><td align=left> 0 </td><td align=left> WB</tr>
<tr valign=top>
<td align=left> </td><td align=left> 0 </td><td align=left> 1 </td><td align=left> WT</tr>
<tr valign=top>
<td align=left> </td><td align=left> 1 </td><td align=left> X </td><td align=left> UC</tr>
<tr valign=top>
<td align=left></tr>
<tr><td colspan="4"><hr></tr>
</tr>

</table>

This table shows MTRR memory types and their properties.
<p>
<table>
<tr valign=top>
<th align=left> </th><th align=left> Cacheable in </th><th align=left>  </th><th align=left> Allows </th><th align=left> Memory</tr>
<tr valign=top>
<th align=left> </th><th align=left> L1 and L2 </th><th align=left> Writeback </th><th align=left> Speculative </th><th align=left> Ordering</tr>
<tr valign=top>
<th align=left>Mnemonic </th><th align=left> Caches </th><th align=left> Cacheable </th><th align=left> Reads </th><th align=left> Model</tr>
<tr><td colspan="5"><hr></tr>
<tr valign=top>
<td align=left>UC </td><td align=left> No </td><td align=left> No </td><td align=left> No </td><td align=left> Strong Ordering</tr>
<tr valign=top>
<td align=left>WC </td><td align=left> No </td><td align=left> No </td><td align=left> Yes </td><td align=left> Weak Ordering</tr>
<tr valign=top>
<td align=left>WT </td><td align=left> Yes </td><td align=left> No </td><td align=left> Yes </td><td align=left> Speculative</tr>
<tr valign=top>
<td align=left> </td><td align=left>  </td><td align=left>  </td><td align=left>  </td><td align=left> Processor Ordering</tr>
<tr valign=top>
<td align=left>WP </td><td align=left> Yes for reads, </td><td align=left> No </td><td align=left> Yes </td><td align=left> Speculative</tr>
<tr valign=top>
<td align=left> </td><td align=left> No for writes </td><td align=left>  </td><td align=left>  </td><td align=left> Processor Ordering</tr>
<tr valign=top>
<td align=left>WB </td><td align=left> Yes </td><td align=left> Yes </td><td align=left> Yes </td><td align=left> Speculative</tr>
<tr valign=top>
<td align=left> </td><td align=left>  </td><td align=left>  </td><td align=left>  </td><td align=left> Processor Ordering</tr>
<tr valign=top>
<td align=left></tr>
<tr><td colspan="5"><hr></tr>
</tr>

</table>

</blockquote><h4>AUTHOR</h4><blockquote><p>
Original port by Hdei Nunoe of Wind River Systems, Alameda, CA.
<p>
</blockquote><h4>SEE ALSO</h4><blockquote><p>
<b><a href="./pc.html#top">pc386/486</a></b>, <i>Tornado User's Guide: Getting Started, </i>
<i>VxWorks Programmer's Guide: Configuration</i>
<i>VxWorks Programmer's Guide: Architecture Appendix</i>
<p>

</blockquote><h4>BIBLIOGRAPHY</h4><blockquote><p>
Refer to the vendor's documentation for the motherboard and
any adaptor cards installed.

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