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<SAMP>`#'</SAMP> in a line of a makefile starts a <EM>comment</EM>.  It and the rest of
the line are ignored, except that a trailing backslash not escaped by
another backslash will continue the comment across multiple lines.
Comments may appear on any of the lines in the makefile, except within a
<CODE>define</CODE> directive, and perhaps within commands (where the shell
decides what is a comment).  A line containing just a comment (with
perhaps spaces before it) is effectively blank, and is ignored.</UL>



<H2><A NAME="SEC14" HREF="make_toc.html#TOC14">What Name to Give Your Makefile</A></H2>
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</P>
<P>
By default, when <CODE>make</CODE> looks for the makefile, it tries the
following names, in order: <TT>`GNUmakefile'</TT>, <TT>`makefile'</TT>
and <TT>`Makefile'</TT>.<A NAME="IDX61"></A>
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</P>
<P>
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In most cases you should call your makefile either <TT>`makefile'</TT> or
<TT>`Makefile'</TT>.  (We recommend <TT>`Makefile'</TT> because it appears
prominently near the beginning of a directory listing, right near other
important files such as <TT>`README'</TT>.)  The first name checked,
<TT>`GNUmakefile'</TT>, is not recommended for most makefiles.  You should
use this name if you have a makefile that is specific to GNU
<CODE>make</CODE>, and will not be understood by other versions of
<CODE>make</CODE>.  Other <CODE>make</CODE> programs look for <TT>`makefile'</TT> and
<TT>`Makefile'</TT>, but not <TT>`GNUmakefile'</TT>.

</P>
<P>
If <CODE>make</CODE> finds none of these names, it does not use any makefile.
Then you must specify a goal with a command argument, and <CODE>make</CODE>
will attempt to figure out how to remake it using only its built-in
implicit rules.  See section <A HREF="make.html#SEC86">Using Implicit Rules</A>.

</P>
<P>
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If you want to use a nonstandard name for your makefile, you can specify
the makefile name with the <SAMP>`-f'</SAMP> or <SAMP>`--file'</SAMP> option.  The
arguments <SAMP>`-f <VAR>name</VAR>'</SAMP> or <SAMP>`--file=<VAR>name</VAR>'</SAMP> tell
<CODE>make</CODE> to read the file <VAR>name</VAR> as the makefile.  If you use
more than one <SAMP>`-f'</SAMP> or <SAMP>`--file'</SAMP> option, you can specify several
makefiles.  All the makefiles are effectively concatenated in the order
specified.  The default makefile names <TT>`GNUmakefile'</TT>,
<TT>`makefile'</TT> and <TT>`Makefile'</TT> are not checked automatically if you
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<H2><A NAME="SEC15" HREF="make_toc.html#TOC15">Including Other Makefiles</A></H2>
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</P>
<P>
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The <CODE>include</CODE> directive tells <CODE>make</CODE> to suspend reading the
current makefile and read one or more other makefiles before continuing.
The directive is a line in the makefile that looks like this:

</P>

<PRE>
include <VAR>filenames</VAR>...
</PRE>

<P>
<VAR>filenames</VAR> can contain shell file name patterns.
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</P>
<P>
Extra spaces are allowed and ignored at the beginning of the line, but
a tab is not allowed.  (If the line begins with a tab, it will be
considered a command line.)  Whitespace is required between
<CODE>include</CODE> and the file names, and between file names; extra
whitespace is ignored there and at the end of the directive.  A
comment starting with <SAMP>`#'</SAMP> is allowed at the end of the line.  If
the file names contain any variable or function references, they are
expanded.  See section <A HREF="make.html#SEC55">How to Use Variables</A>.

</P>
<P>
For example, if you have three <TT>`.mk'</TT> files, <TT>`a.mk'</TT>, 
<TT>`b.mk'</TT>, and <TT>`c.mk'</TT>, and <CODE>$(bar)</CODE> expands to
<CODE>bish bash</CODE>, then the following expression

</P>

<PRE>
include foo *.mk $(bar)
</PRE>

<P>
is equivalent to

</P>

<PRE>
include foo a.mk b.mk c.mk bish bash
</PRE>

<P>
When <CODE>make</CODE> processes an <CODE>include</CODE> directive, it suspends
reading of the containing makefile and reads from each listed file in
turn.  When that is finished, <CODE>make</CODE> resumes reading the
makefile in which the directive appears.

</P>
<P>
One occasion for using <CODE>include</CODE> directives is when several programs,
handled by individual makefiles in various directories, need to use a
common set of variable definitions 
(see section <A HREF="make.html#SEC62">Setting Variables</A>) or pattern rules
(see section <A HREF="make.html#SEC91">Defining and Redefining Pattern Rules</A>).

</P>
<P>
Another such occasion is when you want to generate dependencies from
source files automatically; the dependencies can be put in a file that
is included by the main makefile.  This practice is generally cleaner
than that of somehow appending the dependencies to the end of the main
makefile as has been traditionally done with other versions of
<CODE>make</CODE>.  See section <A HREF="make.html#SEC41">Generating Dependencies Automatically</A>.
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</P>
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If any of the specified filenames does not start with a slash, and the file is not
found in the current directory, several other directories are searched.
First, any directories you have specified with the <SAMP>`-I'</SAMP> or
with the <SAMP>`--include-dir'</SAMP> option are searched
(see section <A HREF="make.html#SEC85">Summary of Options</A>).
Then the following directories (if they exist)
are searched, in this order:

</P>

<UL>
<LI><TT>`<VAR>prefix</VAR>/include'</TT>

      (normally <TT>`/usr/local/include'</TT>)
<LI><TT>`/usr/gnu/include'</TT>,

<LI><TT>`/usr/local/include'</TT>, <TT>`/usr/include'</TT>.

</UL>

<P>
If an included makefile cannot be found in any of these directories, a
warning message is generated, but it is not an immediately fatal error;
processing of the makefile containing the <CODE>include</CODE> continues.
Once it has finished reading makefiles, <CODE>make</CODE> will try to remake
any that are out of date or don't exist.
See section <A HREF="make.html#SEC17">How Makefiles Are Remade</A>.
Only after it has tried to find a way to remake a makefile and failed,
will <CODE>make</CODE> diagnose the missing makefile as a fatal error.

</P>
<P>
If you want <CODE>make</CODE> to simply ignore a makefile which does not exist
and cannot be remade, with no error message, use the <CODE>-include</CODE>
directive instead of <CODE>include</CODE>, like this:

</P>

<PRE>
-include <VAR>filenames</VAR>...
</PRE>

<P>
This is acts like <CODE>include</CODE> in every way except that there is no
error (not even a warning) if any of the <VAR>filenames</VAR> do not exist.

</P>


<H2><A NAME="SEC16" HREF="make_toc.html#TOC16">The Variable <CODE>MAKEFILES</CODE></A></H2>
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</P>
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If the environment variable <CODE>MAKEFILES</CODE> is defined, <CODE>make</CODE>
considers its value as a list of names (separated by whitespace) of
additional makefiles to be read before the others.  This works much like
the <CODE>include</CODE> directive: various directories are searched for those
files (see section <A HREF="make.html#SEC15">Including Other Makefiles</A>).  In addition, the
default goal is never taken from one of these makefiles and it is not an
error if the files listed in <CODE>MAKEFILES</CODE> are not found.
</P>
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The main use of <CODE>MAKEFILES</CODE> is in communication between recursive
invocations of <CODE>make</CODE> (see section <A HREF="make.html#SEC48">Recursive Use of <CODE>make</CODE></A>).  It usually is not desirable to set the environment
variable before a top-level invocation of <CODE>make</CODE>, because it is
usually better not to mess with a makefile from outside.  However, if
you are running <CODE>make</CODE> without a specific makefile, a makefile in
<CODE>MAKEFILES</CODE> can do useful things to help the built-in implicit
rules work better, such as defining search paths (see section <A HREF="make.html#SEC25">Searching Directories for Dependencies</A>).

</P>
<P>
Some users are tempted to set <CODE>MAKEFILES</CODE> in the environment
automatically on login, and program makefiles to expect this to be done.
This is a very bad idea, because such makefiles will fail to work if run by
anyone else.  It is much better to write explicit <CODE>include</CODE> directives
in the makefiles.  See section <A HREF="make.html#SEC15">Including Other Makefiles</A>.

</P>


<H2><A NAME="SEC17" HREF="make_toc.html#TOC17">How Makefiles Are Remade</A></H2>

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Sometimes makefiles can be remade from other files, such as RCS or SCCS
files.  If a makefile can be remade from other files, you probably want
<CODE>make</CODE> to get an up-to-date version of the makefile to read in.

</P>
<P>
To this end, after reading in all makefiles, <CODE>make</CODE> will consider
each as a goal target and attempt to update it.  If a makefile has a
rule which says how to update it (found either in that very makefile or
in another one) or if an implicit rule applies to it (see section <A HREF="make.html#SEC86">Using Implicit Rules</A>), it will be updated if necessary.  After
all makefiles have been checked, if any have actually been changed,
<CODE>make</CODE> starts with a clean slate and reads all the makefiles over
again.  (It will also attempt to update each of them over again, but
normally this will not change them again, since they are already up to
date.)
</P>
<P>
If the makefiles specify a double-colon rule to remake a file with
commands but no dependencies, that file will always be remade
(see section <A HREF="make.html#SEC40">Double-Colon Rules</A>).  In the case of makefiles, a makefile that has a
double-colon rule with commands but no dependencies will be remade every
time <CODE>make</CODE> is run, and then again after <CODE>make</CODE> starts over
and reads the makefiles in again.  This would cause an infinite loop:
<CODE>make</CODE> would constantly remake the makefile, and never do anything
else.  So, to avoid this, <CODE>make</CODE> will <STRONG>not</STRONG> attempt to
remake makefiles which are specified as double-colon targets but have no
dependencies.
</P>
<P>
If you do not specify any makefiles to be read with <SAMP>`-f'</SAMP> or
<SAMP>`--file'</SAMP> options, <CODE>make</CODE> will try the default makefile names;
see section <A HREF="make.html#SEC14">What Name to Give Your Makefile</A>.  Unlike
makefiles explicitly requested with <SAMP>`-f'</SAMP> or <SAMP>`--file'</SAMP> options,
<CODE>make</CODE> is not certain that these makefiles should exist.  However,
if a default makefile does not exist but can be created by running
<CODE>make</CODE> rules, you probably want the rules to be run so that the
makefile can be used.

</P>
<P>
Therefore, if none of the default makefiles exists, <CODE>make</CODE> will try
to make each of them in the same order in which they are searched for
(see section <A HREF="make.html#SEC14">What Name to Give Your Makefile</A>)
until it succeeds in making one, or it runs out of names to try.  Note
that it is not an error if <CODE>make</CODE> cannot find or make any makefile;
a makefile is not always necessary.
</P>
<P>
When you use the <SAMP>`-t'</SAMP> or <SAMP>`--touch'</SAMP> option
(see section <A HREF="make.html#SEC81">Instead of Executing the Commands</A>),
you would not want to use an out-of-date makefile to decide which
targets to touch.  So the <SAMP>`-t'</SAMP> option has no effect on updating
makefiles; they are really updated even if <SAMP>`-t'</SAMP> is specified.
Likewise, <SAMP>`-q'</SAMP> (or <SAMP>`--question'</SAMP>) and <SAMP>`-n'</SAMP> (or
<SAMP>`--just-print'</SAMP>) do not prevent updating of makefiles, because an
out-of-date makefile would result in the wrong output for other targets.
Thus, <SAMP>`make -f mfile -n foo'</SAMP> will update <TT>`mfile'</TT>, read it in,
and then print the commands to update <TT>`foo'</TT> and its dependencies
without running them.  The commands printed for <TT>`foo'</TT> will be those
specified in the updated contents of <TT>`mfile'</TT>.

</P>
<P>
However, on occasion you might actually wish to prevent updating of even
the makefiles.  You can do this by specifying the makefiles as goals in
the command line as well as specifying them as makefiles.  When the
makefile name is specified explicitly as a goal, the options <SAMP>`-t'</SAMP>
and so on do apply to them.

</P>
<P>
Thus, <SAMP>`make -f mfile -n mfile foo'</SAMP> would read the makefile
<TT>`mfile'</TT>, print the commands needed to update it without actually
running them, and then print the commands needed to update <TT>`foo'</TT>
without running them.  The commands for <TT>`foo'</TT> will be those
specified by the existing contents of <TT>`mfile'</TT>.

</P>


<H2><A NAME="SEC18" HREF="make_toc.html#TOC18">Overriding Part of Another Makefile</A></H2>

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Sometimes it is useful to have a makefile that is mostly just like
another makefile.  You can often use the <SAMP>`include'</SAMP> directive to
include one in the other, and add more targets or variable definitions.
However, if the two makefiles give different commands for the same
target, <CODE>make</CODE> will not let you just do this.  But there is another way.

</P>
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In the containing makefile (the one that wants to include the other),
you can use a match-anything pattern rule to say that to remake any
target that cannot be made from the information in the containing
makefile, <CODE>make</CODE> should look in another makefile.
See section <A HREF="make.html#SEC91">Defining and Redefining Pattern Rules</A>, for more information on pattern rules.

</P>
<P>
For example, if you have a makefile called <TT>`Makefile'</TT> that says how
to make the target <SAMP>`foo'</SAMP> (and other targets), you can write a
makefile called <TT>`GNUmakefile'</TT> that contains:

</P>

<PRE>
foo:
        frobnicate &#62; foo

%: force
        @$(MAKE) -f Makefile $@
force: ;
</PRE>

<P>
If you say <SAMP>`make foo'</SAMP>, <CODE>make</CODE> will find <TT>`GNUmakefile'</TT>,
read it, and see that to make <TT>`foo'</TT>, it needs to run the command
<SAMP>`frobnicate &#62; foo'</SAMP>.  If you say <SAMP>`make bar'</SAMP>, <CODE>make</CODE> will
find no way to make <TT>`bar'</TT> in <TT>`GNUmakefile'</TT>, so it will use the
commands from the pattern rule: <SAMP>`make -f Makefile bar'</SAMP>.  If
<TT>`Makefile'</TT> provides a rule for updating <TT>`bar'</TT>, <CODE>make</CODE>
will apply the rule.  And likewise for any other target that
<TT>`GNUmakefile'</TT> does not say how to make.

</P>
<P>
The way this works is that the pattern rule has a pattern of just
<SAMP>`%'</SAMP>, so it matches any target whatever.  The rule specifies a
dependency <TT>`force'</TT>, to guarantee that the commands will be run even
if the target file already exists.  We give <TT>`force'</TT> target empty
commands to prevent <CODE>make</CODE> from searching for an implicit rule to
build it--otherwise it would apply the same match-anything rule to
<TT>`force'</TT> itself and create a dependency loop!

</P>


<H1><A NAME="SEC19" HREF="make_toc.html#TOC19">Writing Rules</A></H1>
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