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is to run the specified commands.  Targets that do not refer to files
but are just actions are called <EM>phony targets</EM>.  See section <A HREF="make.html#SEC31">Phony Targets</A>, for information about this kind of target.  See section <A HREF="make.html#SEC46">Errors in Commands</A>, to see how to cause <CODE>make</CODE> to ignore errors
from <CODE>rm</CODE> or any other command.
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</P>


<H2><A NAME="SEC7" HREF="make_toc.html#TOC7">How <CODE>make</CODE> Processes a Makefile</A></H2>
<P>
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</P>
<P>
By default, <CODE>make</CODE> starts with the first rule (not counting rules
whose target names start with <SAMP>`.'</SAMP>).  This is called the
<EM>default goal</EM>.  (<EM>Goals</EM> are the targets that <CODE>make</CODE>
strives ultimately to update.  See section <A HREF="make.html#SEC80">Arguments to Specify the Goals</A>.)
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</P>
<P>
In the simple example of the previous section, the default goal is to
update the executable program <TT>`edit'</TT>; therefore, we put that rule
first.
Thus, when you give the command:

</P>

<PRE>
make
</PRE>

<P>
<CODE>make</CODE> reads the makefile in the current directory and begins by
processing the first rule.  In the example, this rule is for relinking
<TT>`edit'</TT>; but before <CODE>make</CODE> can fully process this rule, it
must process the rules for the files that <TT>`edit'</TT> depends on,
which in this case are the object files.  Each of these files is
processed according to its own rule.  These rules say to update each
<SAMP>`.o'</SAMP> file by compiling its source file.  The recompilation must
be done if the source file, or any of the header files named as
dependencies, is more recent than the object file, or if the object
file does not exist.

</P>
<P>
The other rules are processed because their targets appear as
dependencies of the goal.  If some other rule is not depended on by the
goal (or anything it depends on, etc.), that rule is not processed,
unless you tell <CODE>make</CODE> to do so (with a command such as
<CODE>make clean</CODE>).

</P>
<P>
Before recompiling an object file, <CODE>make</CODE> considers updating its
dependencies, the source file and header files.  This makefile does not
specify anything to be done for them--the <SAMP>`.c'</SAMP> and <SAMP>`.h'</SAMP> files
are not the targets of any rules--so <CODE>make</CODE> does nothing for these
files.  But <CODE>make</CODE> would update automatically generated C programs,
such as those made by Bison or Yacc, by their own rules at this time.

</P>
<P>
After recompiling whichever object files need it, <CODE>make</CODE> decides
whether to relink <TT>`edit'</TT>.  This must be done if the file
<TT>`edit'</TT> does not exist, or if any of the object files are newer than
it.  If an object file was just recompiled, it is now newer than
<TT>`edit'</TT>, so <TT>`edit'</TT> is relinked.
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</P>
<P>
Thus, if we change the file <TT>`insert.c'</TT> and run <CODE>make</CODE>,
<CODE>make</CODE> will compile that file to update <TT>`insert.o'</TT>, and then
link <TT>`edit'</TT>.  If we change the file <TT>`command.h'</TT> and run
<CODE>make</CODE>, <CODE>make</CODE> will recompile the object files <TT>`kbd.o'</TT>,
<TT>`command.o'</TT> and <TT>`files.o'</TT> and then link the file <TT>`edit'</TT>.

</P>


<H2><A NAME="SEC8" HREF="make_toc.html#TOC8">Variables Make Makefiles Simpler</A></H2>
<P>
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</P>
<P>
In our example, we had to list all the object files twice in the rule for
<TT>`edit'</TT> (repeated here):

</P>

<PRE>
edit : main.o kbd.o command.o display.o \
              insert.o search.o files.o utils.o
        cc -o edit main.o kbd.o command.o display.o \
                   insert.o search.o files.o utils.o
</PRE>

<P>
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Such duplication is error-prone; if a new object file is added to the
system, we might add it to one list and forget the other.  We can eliminate
the risk and simplify the makefile by using a variable.  <EM>Variables</EM>
allow a text string to be defined once and substituted in multiple places
later (see section <A HREF="make.html#SEC55">How to Use Variables</A>).

</P>
<P>
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It is standard practice for every makefile to have a variable named
<CODE>objects</CODE>, <CODE>OBJECTS</CODE>, <CODE>objs</CODE>, <CODE>OBJS</CODE>, <CODE>obj</CODE>,
or <CODE>OBJ</CODE> which is a list of all object file names.  We would
define such a variable <CODE>objects</CODE> with a line like this in the
makefile:
</P>

<PRE>
objects = main.o kbd.o command.o display.o \
          insert.o search.o files.o utils.o
</PRE>

<P>
Then, each place we want to put a list of the object file names, we can
substitute the variable's value by writing <SAMP>`$(objects)'</SAMP>
(see section <A HREF="make.html#SEC55">How to Use Variables</A>).  

</P>
<P>
Here is how the complete simple makefile looks when you use a variable
for the object files:

</P>

<PRE>
objects = main.o kbd.o command.o display.o \
          insert.o search.o files.o utils.o

edit : $(objects)
        cc -o edit $(objects)
main.o : main.c defs.h
        cc -c main.c
kbd.o : kbd.c defs.h command.h
        cc -c kbd.c
command.o : command.c defs.h command.h
        cc -c command.c
display.o : display.c defs.h buffer.h
        cc -c display.c
insert.o : insert.c defs.h buffer.h
        cc -c insert.c
search.o : search.c defs.h buffer.h
        cc -c search.c
files.o : files.c defs.h buffer.h command.h
        cc -c files.c
utils.o : utils.c defs.h
        cc -c utils.c
clean :
        rm edit $(objects)
</PRE>



<H2><A NAME="SEC9" HREF="make_toc.html#TOC9">Letting <CODE>make</CODE> Deduce the Commands</A></H2>
<P>
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</P>
<P>
It is not necessary to spell out the commands for compiling the individual
C source files, because <CODE>make</CODE> can figure them out: it has an
<EM>implicit rule</EM> for updating a <SAMP>`.o'</SAMP> file from a correspondingly
named <SAMP>`.c'</SAMP> file using a <SAMP>`cc -c'</SAMP> command.  For example, it will
use the command <SAMP>`cc -c main.c -o main.o'</SAMP> to compile <TT>`main.c'</TT> into
<TT>`main.o'</TT>.  We can therefore omit the commands from the rules for the
object files.  See section <A HREF="make.html#SEC86">Using Implicit Rules</A>.
</P>
<P>
When a <SAMP>`.c'</SAMP> file is used automatically in this way, it is also
automatically added to the list of dependencies.  We can therefore omit
the <SAMP>`.c'</SAMP> files from the dependencies, provided we omit the commands.

</P>
<P>
Here is the entire example, with both of these changes, and a variable
<CODE>objects</CODE> as suggested above:

</P>

<PRE>
objects = main.o kbd.o command.o display.o \
          insert.o search.o files.o utils.o

edit : $(objects)
        cc -o edit $(objects)

main.o : defs.h
kbd.o : defs.h command.h
command.o : defs.h command.h
display.o : defs.h buffer.h
insert.o : defs.h buffer.h
search.o : defs.h buffer.h
files.o : defs.h buffer.h command.h
utils.o : defs.h

.PHONY : clean
clean :
        -rm edit $(objects)
</PRE>

<P>
This is how we would write the makefile in actual practice.  (The
complications associated with <SAMP>`clean'</SAMP> are described elsewhere.
See section <A HREF="make.html#SEC31">Phony Targets</A>, and section <A HREF="make.html#SEC46">Errors in Commands</A>.)

</P>
<P>
Because implicit rules are so convenient, they are important.  You
will see them used frequently.
</P>


<H2><A NAME="SEC10" HREF="make_toc.html#TOC10">Another Style of Makefile</A></H2>
<P>
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</P>
<P>
When the objects of a makefile are created only by implicit rules, an
alternative style of makefile is possible.  In this style of makefile,
you group entries by their dependencies instead of by their targets.
Here is what one looks like:

</P>

<PRE>
objects = main.o kbd.o command.o display.o \
          insert.o search.o files.o utils.o

edit : $(objects)
        cc -o edit $(objects)

$(objects) : defs.h
kbd.o command.o files.o : command.h
display.o insert.o search.o files.o : buffer.h
</PRE>

<P>
Here <TT>`defs.h'</TT> is given as a dependency of all the object files;
<TT>`command.h'</TT> and <TT>`buffer.h'</TT> are dependencies of the specific
object files listed for them.

</P>
<P>
Whether this is better is a matter of taste: it is more compact, but some
people dislike it because they find it clearer to put all the information
about each target in one place.

</P>


<H2><A NAME="SEC11" HREF="make_toc.html#TOC11">Rules for Cleaning the Directory</A></H2>
<P>
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</P>
<P>
Compiling a program is not the only thing you might want to write rules
for.  Makefiles commonly tell how to do a few other things besides
compiling a program: for example, how to delete all the object files
and executables so that the directory is <SAMP>`clean'</SAMP>.

</P>
<P>
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Here is how we
could write a <CODE>make</CODE> rule for cleaning our example editor:

</P>

<PRE>
clean:
        rm edit $(objects)
</PRE>

<P>
In practice, we might want to write the rule in a somewhat more
complicated manner to handle unanticipated situations.  We would do this:

</P>

<PRE>
.PHONY : clean
clean :
        -rm edit $(objects)
</PRE>

<P>
This prevents <CODE>make</CODE> from getting confused by an actual file
called <TT>`clean'</TT> and causes it to continue in spite of errors from
<CODE>rm</CODE>.  (See section <A HREF="make.html#SEC31">Phony Targets</A>, and section <A HREF="make.html#SEC46">Errors in Commands</A>.)

</P>
<P>
A rule such as this should not be placed at the beginning of the
makefile, because we do not want it to run by default!  Thus, in the
example makefile, we want the rule for <CODE>edit</CODE>, which recompiles
the editor, to remain the default goal.

</P>
<P>
Since <CODE>clean</CODE> is not a dependency of <CODE>edit</CODE>, this rule will not
run at all if we give the command <SAMP>`make'</SAMP> with no arguments.  In
order to make the rule run, we have to type <SAMP>`make clean'</SAMP>.
See section <A HREF="make.html#SEC78">How to Run <CODE>make</CODE></A>.

</P>


<H1><A NAME="SEC12" HREF="make_toc.html#TOC12">Writing Makefiles</A></H1>

<P>
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The information that tells <CODE>make</CODE> how to recompile a system comes from
reading a data base called the <EM>makefile</EM>.

</P>



<H2><A NAME="SEC13" HREF="make_toc.html#TOC13">What Makefiles Contain</A></H2>

<P>
Makefiles contain five kinds of things: <EM>explicit rules</EM>,
<EM>implicit rules</EM>, <EM>variable definitions</EM>, <EM>directives</EM>,
and <EM>comments</EM>.  Rules, variables, and directives are described at
length in later chapters.
</P>

<UL>
<LI>

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An <EM>explicit rule</EM> says when and how to remake one or more files,
called the rule's targets.  It lists the other files that the targets
<EM>depend on</EM>, and may also give commands to use to create or update
the targets.  See section <A HREF="make.html#SEC19">Writing Rules</A>.

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<LI>

An <EM>implicit rule</EM> says when and how to remake a class of files
based on their names.  It describes how a target may depend on a file
with a name similar to the target and gives commands to create or
update such a target.  See section <A HREF="make.html#SEC86">Using Implicit Rules</A>.

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<LI>

A <EM>variable definition</EM> is a line that specifies a text string
value for a variable that can be substituted into the text later.  The
simple makefile example shows a variable definition for <CODE>objects</CODE>
as a list of all object files (see section <A HREF="make.html#SEC8">Variables Make Makefiles Simpler</A>).

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<LI>

A <EM>directive</EM> is a command for <CODE>make</CODE> to do something special while
reading the makefile.  These include:


<UL>
<LI>

Reading another makefile (see section <A HREF="make.html#SEC15">Including Other Makefiles</A>).

<LI>

Deciding (based on the values of variables) whether to use or
ignore a part of the makefile (see section <A HREF="make.html#SEC67">Conditional Parts of Makefiles</A>).

<LI>

Defining a variable from a verbatim string containing multiple lines
(see section <A HREF="make.html#SEC65">Defining Variables Verbatim</A>).