io430x13x.h

用单片机实现(载波监听/冲突检测)的功能

#define CLLD_2         (2*0x0200u)  /* Compare latch load sourec : 2 - up/down */
#define CLLD_3         (3*0x0200u)  /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
 

/*-------------------------------------------------------------------------
 *   Basic Clock Module
 *-------------------------------------------------------------------------*/


__no_init volatile union
{
  unsigned char DCOCTL;  /* DCO Clock Frequency Control */ 
  
  struct
  {
    unsigned char MOD0           : 1;  /* Modulation Bit 0 */ 
    unsigned char MOD1           : 1;  /* Modulation Bit 1 */ 
    unsigned char MOD2           : 1;  /* Modulation Bit 2 */ 
    unsigned char MOD3           : 1;  /* Modulation Bit 3 */ 
    unsigned char MOD4           : 1;  /* Modulation Bit 4 */ 
    unsigned char DCO0           : 1;  /* DCO Select Bit 0 */ 
    unsigned char DCO1           : 1;  /* DCO Select Bit 1 */ 
    unsigned char DCO2           : 1;  /* DCO Select Bit 2 */ 
  } DCOCTL_bit;  
} @ 0x0056;


enum {
  MOD0                = 0x0001,
  MOD1                = 0x0002,
  MOD2                = 0x0004,
  MOD3                = 0x0008,
  MOD4                = 0x0010,
  DCO0                = 0x0020,
  DCO1                = 0x0040,
  DCO2                = 0x0080,
};


__no_init volatile union
{
  unsigned char BCSCTL1;  /* Basic Clock System Control 1 */ 
  
  struct
  {
    unsigned char RSEL0          : 1;  /* Range Select Bit 0 */ 
    unsigned char RSEL1          : 1;  /* Range Select Bit 1 */ 
    unsigned char RSEL2          : 1;  /* Range Select Bit 2 */ 
    unsigned char XT5V           : 1;  /* XT5V should always be reset */ 
    unsigned char DIVA0          : 1;  /* ACLK Divider 0 */ 
    unsigned char DIVA1          : 1;  /* ACLK Divider 1 */ 
    unsigned char XTS            : 1;  /* LFXTCLK 0:Low Freq. / 1: High Freq. */ 
    unsigned char XT2OFF         : 1;  /* Enable XT2CLK */ 
  } BCSCTL1_bit;  
} @ 0x0057;


enum {
  RSEL0               = 0x0001,
  RSEL1               = 0x0002,
  RSEL2               = 0x0004,
  XT5V                = 0x0008,
  DIVA0               = 0x0010,
  DIVA1               = 0x0020,
  XTS                 = 0x0040,
  XT2OFF              = 0x0080,
};


__no_init volatile union
{
  unsigned char BCSCTL2;  /* Basic Clock System Control 2 */ 
  
  struct
  {
    unsigned char DCOR           : 1;  /* Enable External Resistor : 1 */ 
    unsigned char DIVS0          : 1;  /* SMCLK Divider 0 */ 
    unsigned char DIVS1          : 1;  /* SMCLK Divider 1 */ 
    unsigned char SELS           : 1;  /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */ 
    unsigned char DIVM0          : 1;  /* CLK Divider 0 */ 
    unsigned char DIVM1          : 1;  /* CLK Divider 1 */ 
    unsigned char SELM0          : 1;  /* MCLK Source Select 0 */ 
    unsigned char SELM1          : 1;  /* MCLK Source Select 1 */ 
  } BCSCTL2_bit;  
} @ 0x0058;


enum {
  DCOR                = 0x0001,
  DIVS0               = 0x0002,
  DIVS1               = 0x0004,
  SELS                = 0x0008,
  DIVM0               = 0x0010,
  DIVM1               = 0x0020,
  SELM0               = 0x0040,
  SELM1               = 0x0080,
};

 
#define __MSP430_HAS_BASIC_CLOCK__ 	/* Definition to show that Module is available */

#define DIVA_0           (0x00)   	/* ACLK Divider 0: /1 */
#define DIVA_1           (0x10)   	/* ACLK Divider 1: /2 */
#define DIVA_2           (0x20)   	/* ACLK Divider 2: /4 */
#define DIVA_3           (0x30)   	/* ACLK Divider 3: /8 */

#define DIVS_0           (0x00)   	/* SMCLK Divider 0: /1 */
#define DIVS_1           (0x02)   	/* SMCLK Divider 1: /2 */
#define DIVS_2           (0x04)   	/* SMCLK Divider 2: /4 */
#define DIVS_3           (0x06)   	/* SMCLK Divider 3: /8 */

#define DIVM_0           (0x00)   	/* MCLK Divider 0: /1 */
#define DIVM_1           (0x10)   	/* MCLK Divider 1: /2 */
#define DIVM_2           (0x20)   	/* MCLK Divider 2: /4 */
#define DIVM_3           (0x30)   	/* MCLK Divider 3: /8 */

#define SELM_0           (0x00)   	/* MCLK Source Select 0: DCOCLK */
#define SELM_1           (0x40)   	/* MCLK Source Select 1: DCOCLK */
#define SELM_2           (0x80)   	/* MCLK Source Select 2: XT2CLK/LFXTCLK */
#define SELM_3           (0xC0)   	/* MCLK Source Select 3: LFXTCLK */
 

/*-------------------------------------------------------------------------
 *   Comparator A
 *-------------------------------------------------------------------------*/


__no_init volatile union
{
  unsigned char CACTL1;  /* Comparator A Control 1 */ 
  
  struct
  {
    unsigned char CAIFG          : 1;  /* Comp. A Interrupt Flag */ 
    unsigned char CAIE           : 1;  /* Comp. A Interrupt Enable */ 
    unsigned char CAIES          : 1;  /* Comp. A Int. Edge Select: 0:rising / 1:falling */ 
    unsigned char CAON           : 1;  /* Comp. A enable */ 
    unsigned char CAREF0         : 1;  /* Comp. A Internal Reference Select 0 */ 
    unsigned char CAREF1         : 1;  /* Comp. A Internal Reference Select 1 */ 
    unsigned char CARSEL         : 1;  /* Comp. A Internal Reference Enable */ 
    unsigned char CAEX           : 1;  /* Comp. A Exchange Inputs */ 
  } CACTL1_bit;  
} @ 0x0059;


enum {
  CAIFG               = 0x0001,
  CAIE                = 0x0002,
  CAIES               = 0x0004,
  CAON                = 0x0008,
  CAREF0              = 0x0010,
  CAREF1              = 0x0020,
  CARSEL              = 0x0040,
  CAEX                = 0x0080,
};


__no_init volatile union
{
  unsigned char CACTL2;  /* Comparator A Control 2 */ 
  
  struct
  {
    unsigned char CAOUT          : 1;  /* Comp. A Output */ 
    unsigned char CAF            : 1;  /* Comp. A Enable Output Filter */ 
    unsigned char P2CA0          : 1;  /* Comp. A Connect External Signal to CA0 : 1 */ 
    unsigned char P2CA1          : 1;  /* Comp. A Connect External Signal to CA1 : 1 */ 
    unsigned char CACTL24        : 1; 
    unsigned char CACTL25        : 1; 
    unsigned char CACTL26        : 1; 
    unsigned char CACTL27        : 1; 
  } CACTL2_bit;  
} @ 0x005A;


enum {
  CAOUT               = 0x0001,
  CAF                 = 0x0002,
  P2CA0               = 0x0004,
  P2CA1               = 0x0008,
  CACTL24             = 0x0010,
  CACTL25             = 0x0020,
  CACTL26             = 0x0040,
  CACTL27             = 0x0080,
};


__no_init volatile union
{
  unsigned char CAPD;  /* Comparator A Port Disable */ 
  
  struct
  {
    unsigned char CAPD0          : 1;  /* Comp. A Disable Input Buffer of Port Register .0 */ 
    unsigned char CAPD1          : 1;  /* Comp. A Disable Input Buffer of Port Register .1 */ 
    unsigned char CAPD2          : 1;  /* Comp. A Disable Input Buffer of Port Register .2 */ 
    unsigned char CAPD3          : 1;  /* Comp. A Disable Input Buffer of Port Register .3 */ 
    unsigned char CAPD4          : 1;  /* Comp. A Disable Input Buffer of Port Register .4 */ 
    unsigned char CAPD5          : 1;  /* Comp. A Disable Input Buffer of Port Register .5 */ 
    unsigned char CAPD6          : 1;  /* Comp. A Disable Input Buffer of Port Register .6 */ 
    unsigned char CAPD7          : 1;  /* Comp. A Disable Input Buffer of Port Register .7 */ 
  } CAPD_bit;  
} @ 0x005B;


enum {
  CAPD0               = 0x0001,
  CAPD1               = 0x0002,
  CAPD2               = 0x0004,
  CAPD3               = 0x0008,
  CAPD4               = 0x0010,
  CAPD5               = 0x0020,
  CAPD6               = 0x0040,
  CAPD7               = 0x0080,
};

 
#define __MSP430_HAS_COMPA__       /* Definition to show that Module is available */

#define CAREF_0          (0x00)    /* Comp. A Int. Ref. Select 0 : Off */
#define CAREF_1          (0x10)    /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
#define CAREF_2          (0x20)    /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
#define CAREF_3          (0x30)    /* Comp. A Int. Ref. Select 3 : Vt*/
 

/*-------------------------------------------------------------------------
 *   ADC12
 *-------------------------------------------------------------------------*/


__no_init volatile union
{
  unsigned short ADC12CTL0;  /* ADC12 Control 0 */ 
  
  struct
  {
    unsigned short ADC12SC       : 1;  /* ADC12 Start Conversion */ 
    unsigned short ENC           : 1;  /* ADC12 Enable Conversion */ 
    unsigned short ADC12TOVIE    : 1;  /* ADC12 Timer Overflow interrupt enable */ 
    unsigned short ADC12OVIE     : 1;  /* ADC12 Overflow interrupt enable */ 
    unsigned short ADC12ON       : 1;  /* ADC12 On/enable */ 
    unsigned short REFON         : 1;  /* ADC12 Reference on */ 
    unsigned short REF2_5V       : 1;  /* ADC12 Ref 0:1.5V / 1:2.5V */ 
    unsigned short MSC           : 1;  /* ADC12 Multiple SampleConversion */ 
    unsigned short SHT0          : 4;  /* ADC12 Sample Hold 0 */ 
    unsigned short SHT1          : 4;  /* ADC12 Sample Hold 1 */ 
  } ADC12CTL0_bit;  
} @ 0x01A0;


enum {
  ADC12SC             = 0x0001,
  ENC                 = 0x0002,
  ADC12TOVIE          = 0x0004,
  ADC12OVIE           = 0x0008,
  ADC12ON             = 0x0010,
  REFON               = 0x0020,
  REF2_5V             = 0x0040,
  MSC                 = 0x0080,
  SHT0                = 0x0800,
  SHT1                = 0x8000,
};


__no_init volatile union
{
  unsigned short ADC12CTL1;  /* ADC12 Control 1 */ 
  
  struct
  {
    unsigned short ADC12BUSY     : 1;  /* ADC12 Busy */ 
    unsigned short CONSEQ        : 2;  /* ADC12 Conversion Sequence Select */ 
    unsigned short ADC12SSEL     : 2;  /* ADC12 Clock Source Select */ 
    unsigned short ADC12DIV      : 3;  /* ADC12 Clock Divider Select */ 
    unsigned short ISSH          : 1;  /* ADC12 Invert Sample Hold Signal */ 
    unsigned short SHP           : 1;  /* ADC12 Sample/Hold Pulse Mode */ 
    unsigned short SHS           : 2;  /* ADC12 Sample/Hold Source */ 
    unsigned short CSTARTADD     : 4;  /* ADC12 Conversion Start Address */ 
  } ADC12CTL1_bit;  
} @ 0x01A2;


enum {
  ADC12BUSY           = 0x0001,
  CONSEQ              = 0x0004,
  ADC12SSEL           = 0x0010,
  ADC12DIV            = 0x0080,
  ISSH                = 0x0100,
  SHP                 = 0x0200,
  SHS                 = 0x0800,
  CSTARTADD           = 0x8000,
};


 /* ADC12 Interrupt Flag */ 
__no_init volatile unsigned short ADC12IFG @ 0x01A4;  
 

 /* ADC12 Interrupt Enable */ 
__no_init volatile unsigned short ADC12IE @ 0x01A6;  
 

 /* ADC12 Interrupt Vector Word */ 
__no_init volatile unsigned short ADC12IV @ 0x01A8;  
 

 /* ADC12 Conversion Memory 0 */ 
__no_init volatile unsigned short ADC12MEM0 @ 0x0140;  
 

 /* ADC12 Conversion Memory 1 */ 
__no_init volatile unsigned short ADC12MEM1 @ 0x0142;  
 

 /* ADC12 Conversion Memory 2 */ 
__no_init volatile unsigned short ADC12MEM2 @ 0x0144;  
 

 /* ADC12 Conversion Memory 3 */ 
__no_init volatile unsigned short ADC12MEM3 @ 0x0146;  
 

 /* ADC12 Conversion Memory 4 */ 
__no_init volatile unsigned short ADC12MEM4 @ 0x0148;  
 

 /* ADC12 Conversion Memory 5 */ 
__no_init volatile unsigned short ADC12MEM5 @ 0x014A;  
 

 /* ADC12 Conversion Memory 6 */ 
__no_init volatile unsigned short ADC12MEM6 @ 0x014C;  
 

 /* ADC12 Conversion Memory 7 */ 
__no_init volatile unsigned short ADC12MEM7 @ 0x014E;  
 

 /* ADC12 Conversion Memory 8 */ 
__no_init volatile unsigned short ADC12MEM8 @ 0x0150;  
 

 /* ADC12 Conversion Memory 9 */ 
__no_init volatile unsigned short ADC12MEM9 @ 0x0152;  
 

 /* ADC12 Conversion Memory 10 */ 
__no_init volatile unsigned short ADC12MEM10 @ 0x0154;  
 

 /* ADC12 Conversion Memory 11 */ 
__no_init volatile unsigned short ADC12MEM11 @ 0x0156;  
 

 /* ADC12 Conversion Memory 12 */ 
__no_init volatile unsigned short ADC12MEM12 @ 0x0158;  
 

 /* ADC12 Conversion Memory 13 */ 
__no_init volatile unsigned short ADC12MEM13 @ 0x015A;  
 

 /* ADC12 Conversion Memory 14 */ 
__no_init volatile unsigned short ADC12MEM14 @ 0x015C;  
 

 /* ADC12 Conversion Memory 15 */ 
__no_init volatile unsigned short ADC12MEM15 @ 0x015E;  
 

__no_init volatile union
{
  unsigned char ADC12MCTL0;  /* ADC12 Memory Control 0 */ 
  
  struct
  {
    unsigned char INCH           : 4; 
    unsigned char SREF           : 3; 
    unsigned char EOS            : 1; 
  } ADC12MCTL0_bit;  
} @ 0x0080;


enum {
  INCH                = 0x0008,
  SREF                = 0x0040,
  EOS                 = 0x0080,
};


__no_init volatile union
{
  unsigned char ADC12MCTL1;  /* ADC12 Memory Control 1 */ 
  
  struct
  {
    unsigned char INCH           : 4; 
    unsigned char SREF           : 3; 
    unsigned char EOS            : 1; 
  } ADC12MCTL1_bit;  
} @ 0x0081;




__no_init volatile union
{
  unsigned char ADC12MCTL2;  /* ADC12 Memory Control 2 */ 
  
  struct
  {
    unsigned char INCH           : 4; 
    unsigned char SREF           : 3; 
    unsigned char EOS            : 1; 
  } ADC12MCTL2_bit;  
} @ 0x0082;




__no_init volatile union
{