📄 io430x13x.h
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__no_init volatile unsigned char U0MCTL @ 0x0073;
/* USART 0 Baud Rate 0 */
__no_init volatile unsigned char U0BR0 @ 0x0074;
/* USART 0 Baud Rate 1 */
__no_init volatile unsigned char U0BR1 @ 0x0075;
/* USART 0 Receive Buffer */
__no_init volatile unsigned __READ char U0RXBUF @ 0x0076;
/* USART 0 Transmit Buffer */
__no_init volatile unsigned char U0TXBUF @ 0x0077;
#define __MSP430_HAS_UART0__ /* Definition to show that Module is available */
/* Alternate register names */
#define UCTL0 U0CTL /* USART 0 Control */
#define UTCTL0 U0TCTL /* USART 0 Transmit Control */
#define URCTL0 U0RCTL /* USART 0 Receive Control */
#define UMCTL0 U0MCTL /* USART 0 Modulation Control */
#define UBR00 U0BR0 /* USART 0 Baud Rate 0 */
#define UBR10 U0BR1 /* USART 0 Baud Rate 1 */
#define RXBUF0 U0RXBUF /* USART 0 Receive Buffer */
#define TXBUF0 U0TXBUF /* USART 0 Transmit Buffer */
#define UCTL0_ U0CTL /* USART 0 Control */
#define UTCTL0_ U0TCTL /* USART 0 Transmit Control */
#define URCTL0_ U0RCTL /* USART 0 Receive Control */
#define UMCTL0_ U0MCTL /* USART 0 Modulation Control */
#define UBR00_ U0BR0 /* USART 0 Baud Rate 0 */
#define UBR10_ U0BR1 /* USART 0 Baud Rate 1 */
#define RXBUF0_ U0RXBUF /* USART 0 Receive Buffer */
#define TXBUF0_ U0TXBUF /* USART 0 Transmit Buffer */
#define UCTL_0 U0CTL /* USART 0 Control */
#define UTCTL_0 U0TCTL /* USART 0 Transmit Control */
#define URCTL_0 U0RCTL /* USART 0 Receive Control */
#define UMCTL_0 U0MCTL /* USART 0 Modulation Control */
#define UBR0_0 U0BR0 /* USART 0 Baud Rate 0 */
#define UBR1_0 U0BR1 /* USART 0 Baud Rate 1 */
#define RXBUF_0 U0RXBUF /* USART 0 Receive Buffer */
#define TXBUF_0 U0TXBUF /* USART 0 Transmit Buffer */
#define UCTL_0_ U0CTL /* USART 0 Control */
#define UTCTL_0_ U0TCTL /* USART 0 Transmit Control */
#define URCTL_0_ U0RCTL /* USART 0 Receive Control */
#define UMCTL_0_ U0MCTL /* USART 0 Modulation Control */
#define UBR0_0_ U0BR0 /* USART 0 Baud Rate 0 */
#define UBR1_0_ U0BR1 /* USART 0 Baud Rate 1 */
#define RXBUF_0_ U0RXBUF /* USART 0 Receive Buffer */
#define TXBUF_0_ U0TXBUF /* USART 0 Transmit Buffer */
/*-------------------------------------------------------------------------
* Timer A3
*-------------------------------------------------------------------------*/
__no_init volatile union
{
unsigned __READ short TAIV; /* Timer A Interrupt Vector Word */
struct
{
unsigned __READ short : 1;
unsigned __READ short IRQVEC : 3;
unsigned __READ short : 12;
} TAIV_bit;
} @ 0x012E;
enum {
IRQVEC = 0x0008,
};
__no_init volatile union
{
unsigned short TACTL; /* Timer A Control */
struct
{
unsigned short TAIFG : 1; /* Timer A counter interrupt flag */
unsigned short TAIE : 1; /* Timer A counter interrupt enable */
unsigned short TACLR : 1; /* Timer A counter clear */
unsigned short : 1;
unsigned short TAMC : 2; /* Timer A mode control 0 */
unsigned short TAID : 2; /* Timer A clock input divider */
unsigned short TASSEL : 2; /* Timer A clock source select */
unsigned short : 6;
} TACTL_bit;
} @ 0x0160;
enum {
TAIFG = 0x0001,
TAIE = 0x0002,
TACLR = 0x0004,
TAMC = 0x0020,
TAID = 0x0080,
TASSEL = 0x0200,
};
__no_init volatile union
{
unsigned short TACCTL0; /* Timer A Capture/Compare Control 0 */
struct
{
unsigned short CCIFG : 1; /* Capture/compare interrupt flag */
unsigned short COV : 1; /* Capture/compare overflow flag */
unsigned short OUT : 1; /* PWM Output signal if output mode 0 */
unsigned short CCI : 1; /* Capture input signal (read) */
unsigned short CCIE : 1; /* Capture/compare interrupt enable */
unsigned short OUTMOD : 3; /* Output mode */
unsigned short CAP : 1; /* Capture mode: 1 /Compare mode : 0 */
unsigned short : 1;
unsigned short SCCI : 1; /* Latched capture signal (read) */
unsigned short SCS : 1; /* Capture sychronize */
unsigned short CCIS : 2; /* Capture input select */
unsigned short CM : 2; /* Capture mode */
} TACCTL0_bit;
} @ 0x0162;
enum {
CCIFG = 0x0001,
COV = 0x0002,
OUT = 0x0004,
CCI = 0x0008,
CCIE = 0x0010,
OUTMOD = 0x0080,
CAP = 0x0100,
SCCI = 0x0400,
SCS = 0x0800,
CCIS = 0x2000,
CM = 0x8000,
};
__no_init volatile union
{
unsigned short TACCTL1; /* Timer A Capture/Compare Control 1 */
struct
{
unsigned short CCIFG : 1; /* Capture/compare interrupt flag */
unsigned short COV : 1; /* Capture/compare overflow flag */
unsigned short OUT : 1; /* PWM Output signal if output mode 0 */
unsigned short CCI : 1; /* Capture input signal (read) */
unsigned short CCIE : 1; /* Capture/compare interrupt enable */
unsigned short OUTMOD : 3; /* Output mode */
unsigned short CAP : 1; /* Capture mode: 1 /Compare mode : 0 */
unsigned short : 1;
unsigned short SCCI : 1; /* Latched capture signal (read) */
unsigned short SCS : 1; /* Capture sychronize */
unsigned short CCIS : 2; /* Capture input select */
unsigned short CM : 2; /* Capture mode */
} TACCTL1_bit;
} @ 0x0164;
__no_init volatile union
{
unsigned short TACCTL2; /* Timer A Capture/Compare Control 2 */
struct
{
unsigned short CCIFG : 1; /* Capture/compare interrupt flag */
unsigned short COV : 1; /* Capture/compare overflow flag */
unsigned short OUT : 1; /* PWM Output signal if output mode 0 */
unsigned short CCI : 1; /* Capture input signal (read) */
unsigned short CCIE : 1; /* Capture/compare interrupt enable */
unsigned short OUTMOD : 3; /* Output mode */
unsigned short CAP : 1; /* Capture mode: 1 /Compare mode : 0 */
unsigned short : 1;
unsigned short SCCI : 1; /* Latched capture signal (read) */
unsigned short SCS : 1; /* Capture sychronize */
unsigned short CCIS : 2; /* Capture input select */
unsigned short CM : 2; /* Capture mode */
} TACCTL2_bit;
} @ 0x0166;
/* Timer A */
__no_init volatile unsigned short TAR @ 0x0170;
/* Timer A Capture/Compare 0 */
__no_init volatile unsigned short TACCR0 @ 0x0172;
/* Timer A Capture/Compare 1 */
__no_init volatile unsigned short TACCR1 @ 0x0174;
/* Timer A Capture/Compare 2 */
__no_init volatile unsigned short TACCR2 @ 0x0176;
#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */
#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
/* Alternate register names */
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
#define CCTL0_ TACCTL0 /* Timer A Capture/Compare Control 0 */
#define CCTL1_ TACCTL1 /* Timer A Capture/Compare Control 1 */
#define CCTL2_ TACCTL2 /* Timer A Capture/Compare Control 2 */
#define CCR0_ TACCR0 /* Timer A Capture/Compare 0 */
#define CCR1_ TACCR1 /* Timer A Capture/Compare 1 */
#define CCR2_ TACCR2 /* Timer A Capture/Compare 2 */
/*-------------------------------------------------------------------------
* Timer B3
*-------------------------------------------------------------------------*/
__no_init volatile union
{
unsigned __READ short TBIV; /* Timer B Interrupt Vector Word */
struct
{
unsigned __READ short : 1;
unsigned __READ short IRQVEC : 3;
unsigned __READ short : 12;
} TBIV_bit;
} @ 0x011E;
__no_init volatile union
{
unsigned short TBCTL; /* Timer B Control */
struct
{
unsigned short TBIFG : 1; /* Timer B interrupt flag */
unsigned short TBIE : 1; /* Timer B interrupt enable */
unsigned short TBCLR : 1; /* Timer B counter clear */
unsigned short : 1;
unsigned short TBMC : 2; /* Timer B mode control */
unsigned short TBID : 2; /* Timer B clock input divider */
unsigned short TBSSEL : 2; /* Timer B Clock source */
unsigned short : 1;
unsigned short TBCNTL : 2; /* Timer B Counter lenght */
unsigned short TBCLGRP : 2; /* Timer B Compare latch load */
unsigned short : 1;
} TBCTL_bit;
} @ 0x0180;
enum {
TBIFG = 0x0001,
TBIE = 0x0002,
TBCLR = 0x0004,
TBMC = 0x0020,
TBID = 0x0080,
TBSSEL = 0x0200,
TBCNTL = 0x1000,
TBCLGRP = 0x4000,
};
__no_init volatile union
{
unsigned short TBCCTL0; /* Timer B Capture/Compare Control 0 */
struct
{
unsigned short CCIFG : 1; /* Capture/compare interrupt flag */
unsigned short COV : 1; /* Capture/compare overflow flag */
unsigned short OUT : 1; /* PWM Output signal if output mode 0 */
unsigned short CCI : 1; /* Capture input signal (read) */
unsigned short CCIE : 1; /* Capture/compare interrupt enable */
unsigned short OUTMOD : 3; /* Output mode 0 */
unsigned short CAP : 1; /* Capture mode: 1 /Compare mode : 0 */
unsigned short CLLD : 2; /* Compare latch load source */
unsigned short SCS : 1; /* Capture sychronize */
unsigned short CCIS : 2; /* Capture input select */
unsigned short CM : 2; /* Capture mode */
} TBCCTL0_bit;
} @ 0x0182;
__no_init volatile union
{
unsigned short TBCCTL1; /* Timer B Capture/Compare Control 1 */
struct
{
unsigned short CCIFG : 1; /* Capture/compare interrupt flag */
unsigned short COV : 1; /* Capture/compare overflow flag */
unsigned short OUT : 1; /* PWM Output signal if output mode 0 */
unsigned short CCI : 1; /* Capture input signal (read) */
unsigned short CCIE : 1; /* Capture/compare interrupt enable */
unsigned short OUTMOD : 3; /* Output mode 0 */
unsigned short CAP : 1; /* Capture mode: 1 /Compare mode : 0 */
unsigned short CLLD : 2; /* Compare latch load source */
unsigned short SCS : 1; /* Capture sychronize */
unsigned short CCIS : 2; /* Capture input select */
unsigned short CM : 2; /* Capture mode */
} TBCCTL1_bit;
} @ 0x0184;
__no_init volatile union
{
unsigned short TBCCTL2; /* Timer B Capture/Compare Control 2 */
struct
{
unsigned short CCIFG : 1; /* Capture/compare interrupt flag */
unsigned short COV : 1; /* Capture/compare overflow flag */
unsigned short OUT : 1; /* PWM Output signal if output mode 0 */
unsigned short CCI : 1; /* Capture input signal (read) */
unsigned short CCIE : 1; /* Capture/compare interrupt enable */
unsigned short OUTMOD : 3; /* Output mode 0 */
unsigned short CAP : 1; /* Capture mode: 1 /Compare mode : 0 */
unsigned short CLLD : 2; /* Compare latch load source */
unsigned short SCS : 1; /* Capture sychronize */
unsigned short CCIS : 2; /* Capture input select */
unsigned short CM : 2; /* Capture mode */
} TBCCTL2_bit;
} @ 0x0186;
/* Timer B */
__no_init volatile unsigned short TBR @ 0x0190;
/* Timer B Capture/Compare 0 */
__no_init volatile unsigned short TBCCR0 @ 0x0192;
/* Timer B Capture/Compare 1 */
__no_init volatile unsigned short TBCCR1 @ 0x0194;
/* Timer B Capture/Compare 2 */
__no_init volatile unsigned short TBCCR2 @ 0x0196;
#define __MSP430_HAS_TB3__ /* Definition to show that Module is available */
#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */
#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */
#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */
#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */
#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */
#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */
#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */
#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */
#define SHR_0 (0*0x2000u) /* Timer B Group: 0 - individually */
#define SHR_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
#define SHR_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
#define SHR_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */
#define TBCLGRP_0 (0*0x2000u) /* Timer B Group: 0 - individually */
#define TBCLGRP_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
#define TBCLGRP_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
#define TBCLGRP_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */
#define CLLD1 (0x0400) /* Compare latch load source 1 */
#define CLLD0 (0x0200) /* Compare latch load source 0 */
#define SLSHR1 (0x0400) /* Compare latch load source 1 */
#define SLSHR0 (0x0200) /* Compare latch load source 0 */
#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */
#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */
#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */
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