jiaotongdeng.hier_info

这程序是利用状态机来控制交通灯verilog码

|jiaotongdeng
ra <= jiaotongdeng_con:inst3.ra
clock => int_div:inst.clock
clock => int_div2:inst1.clock
clr => jiaotongdeng_con:inst3.clr
ya <= jiaotongdeng_con:inst3.ya
ga <= jiaotongdeng_con:inst3.ga
rb <= jiaotongdeng_con:inst3.rb
yb <= jiaotongdeng_con:inst3.yb
gb <= jiaotongdeng_con:inst3.gb
scan[0] <= seg_7:inst4.scan[0]
scan[1] <= seg_7:inst4.scan[1]
scan[2] <= seg_7:inst4.scan[2]
scan[3] <= seg_7:inst4.scan[3]
scan[4] <= seg_7:inst4.scan[4]
scan[5] <= seg_7:inst4.scan[5]
scan[6] <= seg_7:inst4.scan[6]
scan[7] <= seg_7:inst4.scan[7]
seg[0] <= seg_7:inst4.seg[0]
seg[1] <= seg_7:inst4.seg[1]
seg[2] <= seg_7:inst4.seg[2]
seg[3] <= seg_7:inst4.seg[3]
seg[4] <= seg_7:inst4.seg[4]
seg[5] <= seg_7:inst4.seg[5]
seg[6] <= seg_7:inst4.seg[6]
seg[7] <= seg_7:inst4.seg[7]


|jiaotongdeng|jiaotongdeng_con:inst3
clk => ra~reg0.CLK
clk => ya~reg0.CLK
clk => ga~reg0.CLK
clk => rb~reg0.CLK
clk => yb~reg0.CLK
clk => gb~reg0.CLK
clk => qh[3]~reg0.CLK
clk => qh[2]~reg0.CLK
clk => qh[1]~reg0.CLK
clk => qh[0]~reg0.CLK
clk => ql[3]~reg0.CLK
clk => ql[2]~reg0.CLK
clk => ql[1]~reg0.CLK
clk => ql[0]~reg0.CLK
clk => CS~4.IN1
clr => CS~3.OUTPUTSELECT
clr => CS~2.OUTPUTSELECT
clr => CS~1.OUTPUTSELECT
clr => CS~0.OUTPUTSELECT
qh[0] <= qh[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qh[1] <= qh[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qh[2] <= qh[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qh[3] <= qh[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ql[0] <= ql[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ql[1] <= ql[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ql[2] <= ql[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ql[3] <= ql[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ra <= ra~reg0.DB_MAX_OUTPUT_PORT_TYPE
ya <= ya~reg0.DB_MAX_OUTPUT_PORT_TYPE
ga <= ga~reg0.DB_MAX_OUTPUT_PORT_TYPE
rb <= rb~reg0.DB_MAX_OUTPUT_PORT_TYPE
yb <= yb~reg0.DB_MAX_OUTPUT_PORT_TYPE
gb <= gb~reg0.DB_MAX_OUTPUT_PORT_TYPE


|jiaotongdeng|int_div:inst
clock => count_p[31].CLK
clock => count_p[30].CLK
clock => count_p[29].CLK
clock => count_p[28].CLK
clock => count_p[27].CLK
clock => count_p[26].CLK
clock => count_p[25].CLK
clock => count_p[24].CLK
clock => count_p[23].CLK
clock => count_p[22].CLK
clock => count_p[21].CLK
clock => count_p[20].CLK
clock => count_p[19].CLK
clock => count_p[18].CLK
clock => count_p[17].CLK
clock => count_p[16].CLK
clock => count_p[15].CLK
clock => count_p[14].CLK
clock => count_p[13].CLK
clock => count_p[12].CLK
clock => count_p[11].CLK
clock => count_p[10].CLK
clock => count_p[9].CLK
clock => count_p[8].CLK
clock => count_p[7].CLK
clock => count_p[6].CLK
clock => count_p[5].CLK
clock => count_p[4].CLK
clock => count_p[3].CLK
clock => count_p[2].CLK
clock => count_p[1].CLK
clock => count_p[0].CLK
clock => clk_p_r.CLK
clk_out <= clk_p_r.DB_MAX_OUTPUT_PORT_TYPE


|jiaotongdeng|seg_7:inst4
clk => a[1].CLK
clk => a[0].CLK
scan[0] <= <VCC>
scan[1] <= <VCC>
scan[2] <= <VCC>
scan[3] <= <VCC>
scan[4] <= <VCC>
scan[5] <= <VCC>
scan[6] <= scan[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
scan[7] <= scan[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
qh[0] => Selector2.IN2
qh[1] => Selector1.IN2
qh[2] => Selector0.IN2
qh[3] => Selector3.IN2
ql[0] => Selector2.IN3
ql[1] => Selector1.IN3
ql[2] => Selector0.IN3
ql[3] => Selector3.IN3
seg[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
seg[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
seg[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
seg[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
seg[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
seg[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
seg[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
seg[7] <= <VCC>


|jiaotongdeng|int_div2:inst1
clock => count_p[31].CLK
clock => count_p[30].CLK
clock => count_p[29].CLK
clock => count_p[28].CLK
clock => count_p[27].CLK
clock => count_p[26].CLK
clock => count_p[25].CLK
clock => count_p[24].CLK
clock => count_p[23].CLK
clock => count_p[22].CLK
clock => count_p[21].CLK
clock => count_p[20].CLK
clock => count_p[19].CLK
clock => count_p[18].CLK
clock => count_p[17].CLK
clock => count_p[16].CLK
clock => count_p[15].CLK
clock => count_p[14].CLK
clock => count_p[13].CLK
clock => count_p[12].CLK
clock => count_p[11].CLK
clock => count_p[10].CLK
clock => count_p[9].CLK
clock => count_p[8].CLK
clock => count_p[7].CLK
clock => count_p[6].CLK
clock => count_p[5].CLK
clock => count_p[4].CLK
clock => count_p[3].CLK
clock => count_p[2].CLK
clock => count_p[1].CLK
clock => count_p[0].CLK
clock => clk_p_r.CLK
clk_out <= clk_p_r.DB_MAX_OUTPUT_PORT_TYPE