mifare.c

利用NXP的新一代高集成度的芯片RC500完成Mifare系列卡的读写

		return MI_CHK_FAILED;
    		
	for(i=0;i<6;i++)
		WriteIO(RegFIFOData,MSndBuffer[i]);	 //把密钥和卡号写入FIFO缓冲区
	
	WriteIO(RegCommand,0x0c);     //写命今0C进（01H）命令寄存器
	delay_50us(4);                     //delay 750us 延时
	
	status=ReadIO(RegPrimaryStatus);      
	WriteIO(RegCommand,00);

	if(status<=0x01)
	{
		WriteIO(RegCommand,0x14);       //rc531   authen2 command   0x14
		delay_50us(6);                  //delay_50us(30);// delay 1ms
		status=ReadIO(RegPrimaryStatus);//check   bit crypto1on=1?
		WriteIO(RegCommand,00);
		if(status<=0x01)
		{
			status=ReadIO(RegControl);  //check   bit crypto1on=1?
			if(status&0x08)
				return MI_OK;
		}
	}

	return MI_AUTHERR ;
}

/*************************************************************

        mifare write command 

**************************************************************/ 
char mif_Write( unsigned char blockaddr,unsigned char *W_data)
{
	unsigned char  i,status,ackdata;
    	  
	WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
	WriteIO(RegCommand,00);             // terminate probably running command
	FlushFIFO();  

	status=ReadIO(RegPrimaryStatus);    
	if((status&0x70)!=0x00)
		return MI_CHK_FAILED;
    	
	WriteIO(RegFIFOData,0xa0);          //mifare  write command 0xa0
	WriteIO(RegFIFOData,blockaddr);
		
	WriteIO(RegCommand,0x1e);           //transive  command
	delay_50us(4);                      //delay 1ms
	WriteIO(RegCommand,00);
	ackdata=ReadIO(RegFIFOData);
    	
 	if((ackdata&=0x0f)==0x0a)           //---------send data deal--------------
 	{
		WriteIO(RegCommand,00);         //send idle command
		FlushFIFO();  
      		
		status=ReadIO(RegPrimaryStatus);       
		if(status==0x05)
		{
			for(i=0;i<16;i++)
			WriteIO(RegFIFOData,W_data[i]);  //write data into card
			WriteIO(RegCommand,0x1e);        //transive  command
			//delay_50us(5);                   //40     //delay 2ms
			delay_50us(20);
			WriteIO(RegCommand,00);
	     		
			status=ReadIO(RegFIFOData);
			if(status==0x0a) 
				return MI_OK;                //status==0x0a is right return
		}
	}

	return MI_WRITEERR;	                     //write card wrong return
}

/*************************************************************

            mifare read command

**************************************************************/
char mif_Read(unsigned char blockaddr,unsigned char *mif_data)
{
	unsigned char i ,status;
	unsigned char fifolength;
    	
	WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
	WriteIO(RegCommand,00);             // terminate probably running command
	FlushFIFO();  
	
	status=ReadIO(RegPrimaryStatus);    
	if((status&0x70)!=0x00)
		return MI_CHK_FAILED;
    	
	WriteIO(RegFIFOData,0x30);          //mifare  write command 0xa0
	WriteIO(RegFIFOData,blockaddr);
	WriteIO(RegCommand,0x1e);           //transive  command
	delay_50us(6);                      //delay 1ms
	WriteIO(RegCommand,00);
	fifolength= ReadIO(RegFIFOLength);  //fifo length
	if(fifolength==16)  
	{ 
		for(i=0;i<16;i++)               //copy card block data
		*mif_data++=ReadIO(RegFIFOData);
		return MI_OK;                   //read card success
	}  
	return MI_READERR;  
}

/*************************************************************

            mifare increment   command
        
**************************************************************/
/*
char mif_Increment(unsigned char block_addr, unsigned long val)          
{                           
	unsigned char idata status,ackdata;
	UNLONG idata value;
     	  
	value.btlong=val;
	WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
	WriteIO(RegCommand,00);             // terminate probably running command
	FlushFIFO();  
	status=ReadIO(RegPrimaryStatus);    
	if((status&0x70)!=0x00)
		return MI_CHK_FAILED;
    		
	WriteIO(RegFIFOData,0xc1);          //mifare  Inc command
	WriteIO(RegFIFOData,block_addr);    //card block address
	WriteIO(RegCommand,0x1e);           //transive  command
	delay_50us(4);                      //delay 1ms
	WriteIO(RegCommand,00);
	ackdata=ReadIO(RegFIFOData);
	if(ackdata==0x0a)
	{
		WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
		WriteIO(RegCommand,00);             // terminate probably running command
		delay_50us(4);
		FlushFIFO();  
		status=ReadIO(RegPrimaryStatus);    
		if(status==0x05)
		{
			WriteIO(RegFIFOData,value.stlong.char1);
			WriteIO(RegFIFOData,value.stlong.char2);
			WriteIO(RegFIFOData,value.stlong.char3);
			WriteIO(RegFIFOData,value.stlong.char4);
	     		
			WriteIO(RegCommand,0x1e);       //transive  command
			delay_50us(4);
			WriteIO(RegCommand,00);
			ackdata=ReadIO(RegFIFOLength);
 			
			if (ackdata>0)
			{
				ackdata=ReadIO(RegFIFOData);
				return MI_CODEERR; 
			}
			else
			{	
				status=ReadIO(RegPrimaryStatus);    
						
				return MI_OK;                //right return
			}	
		}
	}
	return MI_INCRERR;
}
*/
/*************************************************************

            mifare  decrement  command
         
**************************************************************/
/*
char mif_Decrement(unsigned char block_addr,  unsigned long val)          
{                    
	unsigned char status,ackdata;
	unsigned int k=0;
	UNLONG idata value;
	value.btlong=val;
     	
	WriteIO(RegChannelRedundancy,0x0f);     // RxCRC and TxCRC disable, parity enable
	WriteIO(RegCommand,00);                 // terminate probably running command
	FlushFIFO();  
	status=ReadIO(RegPrimaryStatus);    
	if((status&0x70)!=0x00)
		return MI_CHK_FAILED;

	WriteIO(RegFIFOData,0xc0);              //mifare  Inc command
	WriteIO(RegFIFOData,block_addr);        //card block address
	WriteIO(RegCommand,0x1e);               //transive  command
	delay_50us(4);                          //delay 1ms
	WriteIO(RegCommand,00);
	ackdata=ReadIO(RegFIFOData);
	if(ackdata==0x0a)
	{
		WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
		WriteIO(RegCommand,00);             // terminate probably running command
		delay_50us(4);
		FlushFIFO();  
		status=ReadIO(RegPrimaryStatus);    
		if(status==0x05)
		{
			WriteIO(RegFIFOData,value.stlong.char1);
			WriteIO(RegFIFOData,value.stlong.char2);
			WriteIO(RegFIFOData,value.stlong.char3);
			WriteIO(RegFIFOData,value.stlong.char4);
			WriteIO(RegCommand,0x1e);       //transive  command
			delay_50us(4);
			WriteIO(RegCommand,00);
			ackdata=ReadIO(RegFIFOLength);
					
			if (ackdata>0)
			{
				ackdata=ReadIO(RegFIFOData);
				return MI_CODEERR; 
			}
			else
			{	
				status=ReadIO(RegPrimaryStatus);    
				return MI_OK;               //right return
			}	
		}			
	}
	return MI_DECRERR;
}
*/
/*************************************************************

                mifare restore command

*************************************************************/
/*
char mif_restore(unsigned char block_addr)
{
	unsigned char status;   

	WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
	WriteIO(RegCommand,00);             // terminate probably running command
	FlushFIFO();  
	status=ReadIO(RegPrimaryStatus);    
	if((status&0x70)!=0x00)
		return MI_CHK_FAILED;

	WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
	WriteIO(RegCommand,00);             // terminate probably running command
	FlushFIFO();  
	status=ReadIO(RegPrimaryStatus);    
	if((status&0x70)!=0x00)
		return MI_CHK_FAILED;
    		
	WriteIO(RegFIFOData,0xc2);          //mifare restore command
	WriteIO(RegFIFOData,block_addr);    //card block address
	WriteIO(RegCommand,0x1e);           //transive  command
	delay_50us(4);                      //delay 1ms
	WriteIO(RegCommand,00);
	status=ReadIO(RegFIFOData);
	if(status==0x0a)
	{
		status=ReadIO(RegSecondaryStatus);    
		if((status&0x0f)==4)            //added
		return MI_OK;     
	}
	return MI_TRANSERR ;                //failure return   
}
*/
/*************************************************************

                mifare transfer command

*************************************************************/
/*
char mif_transfer(unsigned char block_addr)
{
	unsigned char status;

	WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
	WriteIO(RegCommand,00);             // terminate probably running command
	FlushFIFO();  
	status=ReadIO(RegPrimaryStatus);    
	if((status&0x70)!=0x00)
		return MI_CHK_FAILED;

	WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
	WriteIO(RegCommand,00);             // terminate probably running command
	FlushFIFO();  
	status=ReadIO(RegPrimaryStatus);    
	if((status&0x70)!=0x00)
		return MI_CHK_FAILED;

	WriteIO(RegFIFOData,0xb0);          //mifare halt command
	WriteIO(RegFIFOData,block_addr);    //card block address
	WriteIO(RegCommand,0x1e);           //transive  command
	delay_50us(10);                     //delay 1ms
	WriteIO(RegCommand,00);
	status=ReadIO(RegFIFOData);
	if(status==0x0a)
	{
		status=ReadIO(RegSecondaryStatus);    
		if((status&0x0f)==4)            //added
			return MI_OK;     
	}
	return MI_TRANSERR ;                //failure return   
}    
*/ 
/*************************************************************

            mifare halt command

*************************************************************/
/*
char mif_Halt(void)
{
	unsigned char status;
	WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
	WriteIO(RegCommand,00);             // terminate probably running command
	FlushFIFO();  
	status=ReadIO(RegPrimaryStatus);    

	if((status&0x70)!=0x00)
		return MI_CHK_FAILED;
      
	WriteIO(RegFIFOData,0x50);          //mifare halt command
	WriteIO(RegFIFOData,0x0); 
	WriteIO(RegCommand,0x1e);           //transive  command
	delay_50us(4);                      //delay 1ms
	WriteIO(RegCommand,00);
	status=ReadIO(RegFIFOData);

	if(status==0x0a)                    //if status=0x05 command mifare_halt right
            		return MI_OK;     
	return MI_CODEERR;
}
*/
/*****************************************************

          mifare read e2 command

******************************************************/

unsigned char reade2(unsigned char * e2data)
{
	unsigned char i; 
	unsigned char status;
 
	WriteIO(RegInterruptEn,0x7F); // disable all interrupts
	WriteIO(RegInterruptRq,0x7F); // reset interrupt requests
	WriteIO(RegCommand,00);       // terminate probably running command
	status=ReadIO(RegPrimaryStatus);
 
	FlushFIFO();     
	WriteIO(RegFIFOData,0x0);
	WriteIO(RegFIFOData,0);
	//WriteIO(RegFIFOData,8);// 
	WriteIO(RegFIFOData,16);//从FIFO中读取16个字节，主要是想读出序列号
	//WriteIO(RegFIFOData,(PICC_REQBSTD&0x08)|(2&0x07));
	WriteIO(RegCommand,0x03);     //start comman
    
	delay_50us(4);                //delay 500m
	status=ReadIO(RegFIFOLength);
    
	if(status>0)
	{
		for(i=0;i<status;i++)
		{
			e2data[i]=ReadIO(RegFIFOData);	 
		}
		return 0;
	}
	return(status);	  
}