📄 mifare.lst
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509 delay_50us(4); //delay 1ms
510 WriteIO(RegCommand,00);
511 ackdata=ReadIO(RegFIFOData);
512 if(ackdata==0x0a)
513 {
514 WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
515 WriteIO(RegCommand,00); // terminate probably running command
516 delay_50us(4);
517 FlushFIFO();
518 status=ReadIO(RegPrimaryStatus);
519 if(status==0x05)
520 {
521 WriteIO(RegFIFOData,value.stlong.char1);
522 WriteIO(RegFIFOData,value.stlong.char2);
523 WriteIO(RegFIFOData,value.stlong.char3);
524 WriteIO(RegFIFOData,value.stlong.char4);
525
526 WriteIO(RegCommand,0x1e); //transive command
527 delay_50us(4);
528 WriteIO(RegCommand,00);
529 ackdata=ReadIO(RegFIFOLength);
530
531 if (ackdata>0)
532 {
533 ackdata=ReadIO(RegFIFOData);
534 return MI_CODEERR;
535 }
536 else
537 {
538 status=ReadIO(RegPrimaryStatus);
539
540 return MI_OK; //right return
541 }
542 }
543 }
544 return MI_INCRERR;
545 }
546 */
547 /*************************************************************
548
549 mifare decrement command
550
C51 COMPILER V8.08 MIFARE 09/04/2008 10:09:55 PAGE 10
551 **************************************************************/
552 /*
553 char mif_Decrement(unsigned char block_addr, unsigned long val)
554 {
555 unsigned char status,ackdata;
556 unsigned int k=0;
557 UNLONG idata value;
558 value.btlong=val;
559
560 WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
561 WriteIO(RegCommand,00); // terminate probably running command
562 FlushFIFO();
563 status=ReadIO(RegPrimaryStatus);
564 if((status&0x70)!=0x00)
565 return MI_CHK_FAILED;
566
567 WriteIO(RegFIFOData,0xc0); //mifare Inc command
568 WriteIO(RegFIFOData,block_addr); //card block address
569 WriteIO(RegCommand,0x1e); //transive command
570 delay_50us(4); //delay 1ms
571 WriteIO(RegCommand,00);
572 ackdata=ReadIO(RegFIFOData);
573 if(ackdata==0x0a)
574 {
575 WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
576 WriteIO(RegCommand,00); // terminate probably running command
577 delay_50us(4);
578 FlushFIFO();
579 status=ReadIO(RegPrimaryStatus);
580 if(status==0x05)
581 {
582 WriteIO(RegFIFOData,value.stlong.char1);
583 WriteIO(RegFIFOData,value.stlong.char2);
584 WriteIO(RegFIFOData,value.stlong.char3);
585 WriteIO(RegFIFOData,value.stlong.char4);
586 WriteIO(RegCommand,0x1e); //transive command
587 delay_50us(4);
588 WriteIO(RegCommand,00);
589 ackdata=ReadIO(RegFIFOLength);
590
591 if (ackdata>0)
592 {
593 ackdata=ReadIO(RegFIFOData);
594 return MI_CODEERR;
595 }
596 else
597 {
598 status=ReadIO(RegPrimaryStatus);
599 return MI_OK; //right return
600 }
601 }
602 }
603 return MI_DECRERR;
604 }
605 */
606 /*************************************************************
607
608 mifare restore command
609
610 *************************************************************/
611 /*
612 char mif_restore(unsigned char block_addr)
C51 COMPILER V8.08 MIFARE 09/04/2008 10:09:55 PAGE 11
613 {
614 unsigned char status;
615
616 WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
617 WriteIO(RegCommand,00); // terminate probably running command
618 FlushFIFO();
619 status=ReadIO(RegPrimaryStatus);
620 if((status&0x70)!=0x00)
621 return MI_CHK_FAILED;
622
623 WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
624 WriteIO(RegCommand,00); // terminate probably running command
625 FlushFIFO();
626 status=ReadIO(RegPrimaryStatus);
627 if((status&0x70)!=0x00)
628 return MI_CHK_FAILED;
629
630 WriteIO(RegFIFOData,0xc2); //mifare restore command
631 WriteIO(RegFIFOData,block_addr); //card block address
632 WriteIO(RegCommand,0x1e); //transive command
633 delay_50us(4); //delay 1ms
634 WriteIO(RegCommand,00);
635 status=ReadIO(RegFIFOData);
636 if(status==0x0a)
637 {
638 status=ReadIO(RegSecondaryStatus);
639 if((status&0x0f)==4) //added
640 return MI_OK;
641 }
642 return MI_TRANSERR ; //failure return
643 }
644 */
645 /*************************************************************
646
647 mifare transfer command
648
649 *************************************************************/
650 /*
651 char mif_transfer(unsigned char block_addr)
652 {
653 unsigned char status;
654
655 WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
656 WriteIO(RegCommand,00); // terminate probably running command
657 FlushFIFO();
658 status=ReadIO(RegPrimaryStatus);
659 if((status&0x70)!=0x00)
660 return MI_CHK_FAILED;
661
662 WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
663 WriteIO(RegCommand,00); // terminate probably running command
664 FlushFIFO();
665 status=ReadIO(RegPrimaryStatus);
666 if((status&0x70)!=0x00)
667 return MI_CHK_FAILED;
668
669 WriteIO(RegFIFOData,0xb0); //mifare halt command
670 WriteIO(RegFIFOData,block_addr); //card block address
671 WriteIO(RegCommand,0x1e); //transive command
672 delay_50us(10); //delay 1ms
673 WriteIO(RegCommand,00);
674 status=ReadIO(RegFIFOData);
C51 COMPILER V8.08 MIFARE 09/04/2008 10:09:55 PAGE 12
675 if(status==0x0a)
676 {
677 status=ReadIO(RegSecondaryStatus);
678 if((status&0x0f)==4) //added
679 return MI_OK;
680 }
681 return MI_TRANSERR ; //failure return
682 }
683 */
684 /*************************************************************
685
686 mifare halt command
687
688 *************************************************************/
689 /*
690 char mif_Halt(void)
691 {
692 unsigned char status;
693 WriteIO(RegChannelRedundancy,0x0f); // RxCRC and TxCRC disable, parity enable
694 WriteIO(RegCommand,00); // terminate probably running command
695 FlushFIFO();
696 status=ReadIO(RegPrimaryStatus);
697
698 if((status&0x70)!=0x00)
699 return MI_CHK_FAILED;
700
701 WriteIO(RegFIFOData,0x50); //mifare halt command
702 WriteIO(RegFIFOData,0x0);
703 WriteIO(RegCommand,0x1e); //transive command
704 delay_50us(4); //delay 1ms
705 WriteIO(RegCommand,00);
706 status=ReadIO(RegFIFOData);
707
708 if(status==0x0a) //if status=0x05 command mifare_halt right
709 return MI_OK;
710 return MI_CODEERR;
711 }
712 */
713 /*****************************************************
714
715 mifare read e2 command
716
717 ******************************************************/
718
719 unsigned char reade2(unsigned char * e2data)
720 {
721 1 unsigned char i;
722 1 unsigned char status;
723 1
724 1 WriteIO(RegInterruptEn,0x7F); // disable all interrupts
725 1 WriteIO(RegInterruptRq,0x7F); // reset interrupt requests
726 1 WriteIO(RegCommand,00); // terminate probably running command
727 1 status=ReadIO(RegPrimaryStatus);
728 1
729 1 FlushFIFO();
730 1 WriteIO(RegFIFOData,0x0);
731 1 WriteIO(RegFIFOData,0);
732 1 //WriteIO(RegFIFOData,8);//
733 1 WriteIO(RegFIFOData,16);//从FIFO中读取16个字节，主要是想读出序列号
734 1 //WriteIO(RegFIFOData,(PICC_REQBSTD&0x08)|(2&0x07));
735 1 WriteIO(RegCommand,0x03); //start comman
736 1
C51 COMPILER V8.08 MIFARE 09/04/2008 10:09:55 PAGE 13
737 1 delay_50us(4); //delay 500m
738 1 status=ReadIO(RegFIFOLength);
739 1
740 1 if(status>0)
741 1 {
742 2 for(i=0;i<status;i++)
743 2 {
744 3 e2data[i]=ReadIO(RegFIFOData);
745 3 }
746 2 return 0;
747 2 }
748 1 return(status);
749 1 }
750
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 1527 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- 59
IDATA SIZE = ---- 8
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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