📄 mifare.lst
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C51 COMPILER V8.08 MIFARE 09/04/2008 10:09:55 PAGE 1
C51 COMPILER V8.08, COMPILATION OF MODULE MIFARE
OBJECT MODULE PLACED IN MIFARE.OBJ
COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE MIFARE.C ROM(COMPACT) BROWSE DEBUG OBJECTEXTEND
line level source
1 //#include "..\inc\normal.h"
2 #include "mifare.h"
3
4 ///////////////////////////////////////////////////////////////////////////////
5 // G E N E R I C W R I T E
6 ///////////////////////////////////////////////////////////////////////////////
7 void WriteIO(unsigned char Address, unsigned char value)
8 {
9 1 outportb(Gpbase+Address,value);
10 1 }
11
12 ///////////////////////////////////////////////////////////////////////////////
13 // G E N E R I C R E A D
14 ///////////////////////////////////////////////////////////////////////////////
15 unsigned char ReadIO(unsigned char Address)
16 {
17 1 return inportb(Gpbase+Address);
18 1 //return (i);
19 1 }
20
21 ///////////////////////////////////////////////////////////////////////////////
22 // S E T A B I T M A S K
23 ///////////////////////////////////////////////////////////////////////////////
24 char SetBitMask(unsigned char reg,unsigned char mask) //
25 {
26 1 char idata tmp = 0x0;
27 1
28 1 tmp = ReadIO(reg);
29 1 WriteIO(reg,tmp | mask); // set bit mask
30 1 return 0x0;
31 1 }
32
33 ///////////////////////////////////////////////////////////////////////////////
34 // C L E A R A B I T M A S K
35 ///////////////////////////////////////////////////////////////////////////////
36 char ClearBitMask(unsigned char reg,unsigned char mask) //
37 {
38 1 char idata tmp = 0x0;
39 1 tmp = ReadIO(reg);
40 1 WriteIO(reg,tmp & ~mask); // clear bit mask
41 1 return 0x0;
42 1 }
43
44 ///////////////////////////////////////////////////////////////////////////////
45 // delay_50us
46 ///////////////////////////////////////////////////////////////////////////////
47 void delay_50us(unsigned char i)
48 {
49 1 unsigned char idata b;
50 1 b=0x01;
51 1 while(i--)
52 1 {
53 2 while(b--);
54 2 }
55 1 }
C51 COMPILER V8.08 MIFARE 09/04/2008 10:09:55 PAGE 2
56
57 ///////////////////////////////////////////////////////////////////////////////
58 // FlushFIFO
59 ///////////////////////////////////////////////////////////////////////////////
60 void FlushFIFO(void)
61 {
62 1 SetBitMask(RegControl,0x01);
63 1 }
64
65 /****************************************
66
67 RC531
68
69 *****************************************/
70 ///////////////////////////////////////////////////////////////////////////////
71 // M500PcdReset
72 ///////////////////////////////////////////////////////////////////////////////
73 char M500PcdReset(void)
74 {
75 1 char idata status = MI_OK;
76 1 unsigned char Time;
77 1 Time=5000;
78 1 while((ReadIO(RegCommand)&0x3f)!=0)
79 1 {
80 2 Time--;
81 2 if(!Time)
82 2 {
83 3 break;
84 3 }
85 2 }
86 1 WriteIO(RegPage,0x80); // Dummy access in order to determine the bus
87 1 if (ReadIO(RegCommand) != 0x00)
88 1 {
89 2 status = MI_INTERFACEERR;
90 2 }
91 1 WriteIO(RegPage,0x00); // configure to linear address mode
92 1 return status;
93 1 }
94
95 /***************************************************************
96
97 RF I/O RESET FUNCTIONS
98
99 ****************************************************************/
100 void M500PcdRfReset(unsigned char ms)
101 {
102 1 // outport(AUXCON, 0x0083); //After configuration,things is: i/o set 8bit mode
103 1 char idata status = 0;
104 1 if(ms)
105 1 {
106 2 ClearBitMask(RegTxControl,0x03); // Tx2RF-En, Tx1RF-En disablen
107 2 delay_50us(ms*10); // Delay for 1 ms
108 2 SetBitMask(RegTxControl,0x03); // Tx2RF-En, Tx1RF-En enable
109 2 }
110 1 else
111 1 ClearBitMask(RegTxControl,0x03); // Tx2RF-En, Tx1RF-En disablen
112 1 // return status;
113 1 }
114 //**************************************************************************/
115
116 unsigned char M500HostCodeKey(unsigned char *uncoded,unsigned char *coded) // 6 bytes key value uncod
-ed // 12 bytes key value coded
C51 COMPILER V8.08 MIFARE 09/04/2008 10:09:55 PAGE 3
117 {
118 1 unsigned char idata cnt = 0;
119 1 unsigned char idata ln = 0; // low nibble
120 1 unsigned char idata hn = 0; // high nibble
121 1 for (cnt = 0; cnt < 6; cnt++)
122 1 {
123 2 ln = uncoded[cnt] & 0x0F;
124 2 hn = uncoded[cnt] >> 4;
125 2 coded[cnt * 2 + 1] = (~ln << 4) | ln;
126 2 coded[cnt * 2 ] = (~hn << 4) | hn;
127 2 }
128 1 return MI_OK;
129 1 }
130
131 //*************************************************************
132
133 // LOADCONFIG COMMAND
134
135 // initlise rc531 register files and rf signals
136
137 //**************************************************************/
138 char mif_config(void)
139 {
140 1 if(M500PcdReset() ==0)
141 1 {
142 2 WriteIO(RegControl,0x00);
143 2 WriteIO(RegClockQControl,0x0);
144 2 WriteIO(RegClockQControl,0x40);
145 2 delay_50us(4); // wait approximately 100 us - calibration in progress
146 2 ClearBitMask(RegClockQControl,0x40); // clear bit ClkQCalib for
147 2 WriteIO(RegBitPhase,0xAD);
148 2 WriteIO(RegRxThreshold,0x9d);
149 2 WriteIO(RegRxWait,0x06);
150 2 WriteIO(RegRxControl2,0x01);
151 2 WriteIO(RegFIFOLevel,0x04);
152 2 WriteIO(RegTimerControl,0x02); // TStopRxEnd=0,TStopRxBeg=1,
153 2 delay_50us(4);//delay_50us(20); //delay1ms
154 2 WriteIO(RegIRqPinConfig,0x02); // interrupt active low enable
155 2 WriteIO(RegInterruptEn,0x7F); // disable all interrupts
156 2 WriteIO(RegInterruptRq,0x7F); // reset interrupt requests
157 2 M500PcdRfReset(1); // Rf - reset and enable output driver
158 2 return MI_OK;
159 2 }
160 1 else
161 1 return MI_INTERFACEERR ;
162 1 }
163
164 /*********************************************************************
165
166 request COMMAND
167
168 **********************************************************************/
169 char mif_request2(unsigned char mode,unsigned char *atq)
170 {
171 1 unsigned char req_code=0;
172 1 unsigned char m_status;
173 1
174 1 WriteIO(RegControl,0x00);
175 1 if(mode)
176 1 req_code=0x52;
177 1 else
178 1 req_code=0x26;
C51 COMPILER V8.08 MIFARE 09/04/2008 10:09:55 PAGE 4
179 1 WriteIO(RegChannelRedundancy,0x03); // RxCRC and TxCRC disable, parity enable
180 1 ClearBitMask(RegControl,0x01); // disable crypto 1 unit
181 1 WriteIO(RegBitFraming,0x07); // set TxLastBits to 7
182 1 SetBitMask(RegTxControl,0x03); // Tx2RF-En, Tx1RF-En enable
183 1 WriteIO(RegCommand,00); // terminate probably running command
184 1 FlushFIFO();
185 1 m_status=ReadIO(RegPrimaryStatus);
186 1 if((m_status&0x60)!=0x00)
187 1 return MI_CHK_FAILED;
188 1 WriteIO(RegFIFOData,req_code);
189 1 WriteIO(RegCommand,0x1e);
190 1 delay_50us(4); //delay_50us(20); //delay 1ms
191 1 m_status=ReadIO(RegPrimaryStatus);
192 1 WriteIO(RegCommand,00);
193 1 m_status=ReadIO(RegFIFOLength);; //test fifo length
194 1 if(m_status==0x02)
195 1 {
196 2 *atq++=ReadIO(RegFIFOData);
197 2 *atq=ReadIO(RegFIFOData);
198 2 return MI_OK;
199 2 }
200 1 return MI_NOTAGERR; //no card checked
201 1 }
202
203 /*****************************************************
204
205 mifare anticoll command
206
207 ******************************************************/
208 char mif_anticoll(unsigned char bcnt,unsigned char *cardsnr)
209 {
210 1 unsigned char m_status,i,validbit=0;
211 1 unsigned char snrbuffer[5];
212 1 unsigned char snrcnt=0,collcntbits=0,fifolength=0;
213 1 unsigned char colleftbit=0;
214 1 unsigned char checkbcc;
215 1
216 1 WriteIO(RegDecoderControl,0x28); // ZeroAfterColl aktivieren
217 1 ClearBitMask(RegControl,0x08); // disable crypto 1 unit
218 1 WriteIO(RegCommand,00); // terminate probably running command
219 1 FlushFIFO();
220 1
221 1 WriteIO(RegChannelRedundancy,0x03); // RxCRC and TxCRC disable, parity enable
222 1 m_status=ReadIO(RegPrimaryStatus);
223 1
224 1 if((m_status&0x60)!=0x00)
225 1 return MI_CHK_FAILED;
226 1 bcnt=0x20;
227 1 WriteIO(RegFIFOData,0x93);
228 1 WriteIO(RegFIFOData,bcnt);
229 1 WriteIO(RegCommand,0x1e);
230 1 delay_50us(6);//delay_50us(30);
231 1 WriteIO(RegCommand,00);
232 1 for(i=0;i<5;i++)
233 1 snrbuffer[i]=0x00; //clear the snrbuffer
234 1
235 1 collcntbits=ReadIO(RegCollpos); //check collision bit is valid or not
236 1
237 1 fifolength= ReadIO(RegFIFOLength); //fifo length
238 1
239 1 m_status = ReadIO(RegErrorFlag);
240 1 validbit=ReadIO(RegSecondaryStatus); //judge valid bit
C51 COMPILER V8.08 MIFARE 09/04/2008 10:09:55 PAGE 5
241 1 checkbcc=0;
242 1 if((fifolength==0x05)&(collcntbits==0x00))
243 1 {
244 2 for(i=0;i<fifolength;i++)
245 2 {
246 3 cardsnr[i]=ReadIO(RegFIFOData);
247 3 checkbcc^=cardsnr[i];
248 3 }
249 2 if (checkbcc==0)
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