ixsspacc.c

有关ARM开发板上的IXP400网络驱动程序的源码以。

            (IX_SSP_INTERRUPT_DISABLE << IX_SSP_TX_FIFO_INT_ENABLE_LOC);
        IX_OSAL_WRITE_LONG (ixSspCR1Addr, ixSspAccCfgStored.sscr1);
        ixTxFIFOThsldHdlr = NULL;
    } /* end of TRUE == ixSspAccInterruptMode */

    return IX_SSP_SUCCESS;
} /* end of ixSspAccTxFIFOIntDisable */

PUBLIC IX_SSP_STATUS
ixSspAccLoopbackEnable (
    BOOL loopbackEnable)
{
    /* Disallow this function from running if SSP not initialized */
    IX_SSP_INIT_SUCCESS_CHECK("ixSspAccLoopbackEnable", IX_SSP_NOT_INIT);

    /* Write the parameter into the loopback enable bit of SSCR1 register */
    ixSspAccCfgStored.sscr1 =
        (ixSspAccCfgStored.sscr1 & (~IX_SSP_LOOPBACK_ENABLE_MASK)) |
        (loopbackEnable << IX_SSP_LOOPBACK_ENABLE_LOC);
    IX_OSAL_WRITE_LONG (ixSspCR1Addr, ixSspAccCfgStored.sscr1);
    
    return IX_SSP_SUCCESS;
} /* end of ixSspAccLoopbackEnable */

PUBLIC IX_SSP_STATUS
ixSspAccSpiSclkPolaritySet (
    IxSspAccSpiSclkPolarity spiSclkPolaritySelected)
{
    /* Disallow this function from running if SSP not initialized */
    IX_SSP_INIT_SUCCESS_CHECK("ixSspAccSpiSclkPolaritySet", IX_SSP_NOT_INIT);

    /* Check for validity of parameter */
    if(spiSclkPolaritySelected >= INVALID_SPI_POLARITY)
        return IX_SSP_INVALID_SPI_POLARITY_ENUM_VALUE;

    /* Write the parameter into the SPI SCLK Polarity bit of SSCR1 register */
    ixSspAccCfgStored.sscr1 =
        (ixSspAccCfgStored.sscr1 & (~IX_SSP_SPI_SCLK_POLARITY_MASK)) |
        (spiSclkPolaritySelected << IX_SSP_SPI_SCLK_POLARITY_LOC);
    IX_OSAL_WRITE_LONG (ixSspCR1Addr, ixSspAccCfgStored.sscr1);

    return IX_SSP_SUCCESS;
} /* end of ixSspAccSpiSclkPolaritySet */

PUBLIC IX_SSP_STATUS
ixSspAccSpiSclkPhaseSet (
    IxSspAccSpiSclkPhase spiSclkPhaseSelected)
{
    /* Disallow this function from running if SSP not initialized */
    IX_SSP_INIT_SUCCESS_CHECK("ixSspAccSpiSclkPhaseSet", IX_SSP_NOT_INIT);

    /* Check for validity of parameter */
    if(spiSclkPhaseSelected >= INVALID_SPI_PHASE)
        return IX_SSP_INVALID_SPI_PHASE_ENUM_VALUE;

    /* Write the parameter into the SPI SCLK Phase bit of SSCR1 register */
    ixSspAccCfgStored.sscr1 =
        (ixSspAccCfgStored.sscr1 & (~IX_SSP_SPI_SCLK_PHASE_MASK)) |
        (spiSclkPhaseSelected << IX_SSP_SPI_SCLK_PHASE_LOC);
    IX_OSAL_WRITE_LONG (ixSspCR1Addr, ixSspAccCfgStored.sscr1);

    return IX_SSP_SUCCESS;
} /* end of ixSspAccSpiSclkPhaseSet */

PUBLIC IX_SSP_STATUS
ixSspAccMicrowireControlWordSet (
    IxSspAccMicrowireCtlWord microwireCtlWordSelected)
{
    /* Disallow this function from running if SSP not initialized */
    IX_SSP_INIT_SUCCESS_CHECK("ixSspAccMicrowireControlWordSet", IX_SSP_NOT_INIT);

    /* Check for validity of parameter */
    if(microwireCtlWordSelected >= INVALID_MICROWIRE_CTL_WORD)
        return IX_SSP_INVALID_MICROWIRE_CTL_CMD_ENUM_VALUE;

    /* Only allow change if Tx FIFO is empty */
    if(IX_SSP_FIFO_EMPTY != ixSspAccTxFIFOLevelGet())
        return IX_SSP_TX_FIFO_NOT_EMPTY;

    /* Write the parameter into the Microwire Data Size bit of SSCR1 register*/
    ixSspAccCfgStored.sscr1 =
        (ixSspAccCfgStored.sscr1 & (~IX_SSP_MICROWIRE_CTL_WORD_MASK)) |
        (microwireCtlWordSelected << IX_SSP_MICROWIRE_CTL_WORD_LOC);
    IX_OSAL_WRITE_LONG (ixSspCR1Addr, ixSspAccCfgStored.sscr1);

    return IX_SSP_SUCCESS;
} /* end of ixSspAccMicrowireControlWordSet */

PUBLIC IX_SSP_STATUS
ixSspAccTxFIFOThresholdSet (
    IxSspAccFifoThreshold txFIFOThresholdSelected)
{
    /* Disallow this function from running if SSP not initialized */
    IX_SSP_INIT_SUCCESS_CHECK("ixSspAccTxFIFOThresholdSet", IX_SSP_NOT_INIT);

    /* Check for validity of parameter */
    if(txFIFOThresholdSelected >= INVALID_FIFO_TSHLD)
        return IX_SSP_INVALID_TX_FIFO_THRESHOLD_ENUM_VALUE;

    /* Write the parameter into the Tx FIFO threshold bits of SSCR1 register */
    ixSspAccCfgStored.sscr1 =
        (ixSspAccCfgStored.sscr1 & (~IX_SSP_TX_FIFO_THLD_MASK)) |
        (txFIFOThresholdSelected << IX_SSP_TX_FIFO_THLD_LOC);
    IX_OSAL_WRITE_LONG (ixSspCR1Addr, ixSspAccCfgStored.sscr1);

    return IX_SSP_SUCCESS;
} /* end of ixSspAccTxFIFOThresholdSet */

PUBLIC IX_SSP_STATUS
ixSspAccRxFIFOThresholdSet (
    IxSspAccFifoThreshold rxFIFOThresholdSelected)
{
    /* Disallow this function from running if SSP not initialized */
    IX_SSP_INIT_SUCCESS_CHECK("ixSspAccRxFIFOThresholdSet", IX_SSP_NOT_INIT);

    /* Check for validity of parameter */
    if(rxFIFOThresholdSelected >= INVALID_FIFO_TSHLD)
        return IX_SSP_INVALID_RX_FIFO_THRESHOLD_ENUM_VALUE;

    /* Write the parameter into the Rx FIFO threshold bits of SSCR1 register */
    ixSspAccCfgStored.sscr1 =
        (ixSspAccCfgStored.sscr1 & (~IX_SSP_RX_FIFO_THLD_MASK)) |
        (rxFIFOThresholdSelected << IX_SSP_RX_FIFO_THLD_LOC);
    IX_OSAL_WRITE_LONG (ixSspCR1Addr, ixSspAccCfgStored.sscr1);

    return IX_SSP_SUCCESS;
} /* end of ixSspAccRxFIFOThresholdSet */

/**
 * Debug functions
 */

PUBLIC IX_SSP_STATUS
ixSspAccStatsGet (
    IxSspAccStatsCounters *sspStats)
{
    if(NULL == sspStats)
    {
        ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR,
            "ixSspAccStatsGet: stats pointer is NULL.\n",
            0,0,0,0,0,0);
        return IX_SSP_FAIL;
    } /* end of NULL == sspStats */
        
    /* Copy the SSP stats counters to the struct pointer passed in */
    sspStats->ixSspRcvCounter = ixSspAccStatsCounters.ixSspRcvCounter;
    sspStats->ixSspXmitCounter = ixSspAccStatsCounters.ixSspXmitCounter;
    sspStats->ixSspOverflowCounter = ixSspAccStatsCounters.ixSspOverflowCounter;

    return IX_SSP_SUCCESS;
} /* end of ixSspAccStatsGet */

PUBLIC void
ixSspAccStatsReset (
    void)
{
    /* Clear the SSP stats counters to zero */
    ixSspAccStatsCounters.ixSspRcvCounter = 0;
    ixSspAccStatsCounters.ixSspXmitCounter = 0;
    ixSspAccStatsCounters.ixSspOverflowCounter = 0;

    return;
} /* end of ixSspAccStatsReset */

PUBLIC IX_SSP_STATUS
ixSspAccShow (
    void)
{
    IxSspAccStatsCounters sspStats;
    UINT8 TxFIFOLevel;
    UINT8 RxFIFOLevel;

    /* Disallow this function from running further if SSP not initialized */
    IX_SSP_INIT_SUCCESS_CHECK("ixSspAccShow", IX_SSP_NOT_INIT);

    /* Read and display the SSP status */
    ixSspAccStsStored = IX_OSAL_READ_LONG (ixSspSRAddr);

    RxFIFOLevel = ixSspAccRxFIFOLevelGet();
    TxFIFOLevel = ixSspAccTxFIFOLevelGet();
    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
        "Rx FIFO Level  : %d\n", RxFIFOLevel,0,0,0,0,0);
    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
        "Tx FIFO Level  : %d\n", TxFIFOLevel,0,0,0,0,0);
    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
        "1 = YES, 0 = NO\n",0,0,0,0,0,0);
    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
        "Rx FIFO Overrun: %d\n", ((ixSspAccStsStored &
        IX_SSP_RX_FIFO_OVERRUN_MASK) >> IX_SSP_RX_FIFO_OVERRUN_LOC),0,0,0,0,0);
    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
        "SSP Busy: %d\n", ((ixSspAccStsStored & IX_SSP_BUSY_MASK) >>
        IX_SSP_BUSY_LOC),0,0,0,0,0);
    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
        "Rx FIFO Threshold Hit or Above: %d\n",
        ((ixSspAccStsStored & IX_SSP_RX_FIFO_SVC_REQ_MASK) >>
        IX_SSP_RX_FIFO_SVC_REQ_LOC),0,0,0,0,0);
    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
        "Tx FIFO Threshold Hit or Below: %d\n",
        ((ixSspAccStsStored & IX_SSP_TX_FIFO_SVC_REQ_MASK) >>
        IX_SSP_TX_FIFO_SVC_REQ_LOC),0,0,0,0,0);

    /* Read and display the SSP stats counters */
    ixSspAccStatsGet(&sspStats);
    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
        "SSP frames received   : %d\n", sspStats.ixSspRcvCounter,0,0,0,0,0);
    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
        "SSP frames transmitted: %d\n", sspStats.ixSspXmitCounter,0,0,0,0,0);
    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
        "SSP overflow occurence: %d\n", sspStats.ixSspOverflowCounter,0,0,0,0,0);

    return IX_SSP_SUCCESS;
} /* end of ixSspAccShow */

PUBLIC IX_SSP_STATUS
ixSspAccSSPBusyCheck (
    void)
{
    /* Disallow this function from running if SSP not initialized */
    IX_SSP_INIT_SUCCESS_CHECK("ixSspAccSSPBusyCheck", IX_SSP_NOT_INIT);

    /* Read the SSSR to determine the state of the SSP */
    ixSspAccStsStored = IX_OSAL_READ_LONG (ixSspSRAddr);
    /* Return the status of the SSP Port (busy or idle) */
    if(IX_SSP_IS_BUSY ==
        ((ixSspAccStsStored & IX_SSP_BUSY_MASK) >> IX_SSP_BUSY_LOC))
    {
        return IX_SSP_BUSY;
    }
    else
    {
        return IX_SSP_IDLE;
    }
} /* end of ixSspAccSSPBusyCheck */

PUBLIC UINT8
ixSspAccTxFIFOLevelGet (
    void)
{
    /* Disallow this function from running if SSP not initialized */
    IX_SSP_INIT_SUCCESS_CHECK("ixSspAccTxFIFOLevelGet", IX_SSP_FIFO_EMPTY);


    ixSspAccStsStored = IX_OSAL_READ_LONG (ixSspSRAddr);
    /* If the Tx FIFO level is non-zero, the value is the actual level */
    if(IX_SSP_FIFO_FULL_OR_EMPTY !=
        ((ixSspAccStsStored & IX_SSP_TX_FIFO_LVL_MASK) >>
        IX_SSP_TX_FIFO_LVL_LOC))
    {
        return ((ixSspAccStsStored & IX_SSP_TX_FIFO_LVL_MASK) >>
                IX_SSP_TX_FIFO_LVL_LOC);
    }

    /* If the Tx FIFO level is zero, the value can be 0 (empty) or 16 (full)
    depending on the Tx FIFO Not Full bit */
    if(IX_SSP_TX_FIFO_FULL ==
        ((ixSspAccStsStored & IX_SSP_TX_FIFO_NOT_FULL_MASK) >>
        IX_SSP_TX_FIFO_NOT_FULL_LOC))
    {
        return IX_SSP_FIFO_FULL;
    }
    else
    {
        return IX_SSP_FIFO_EMPTY;
    }
} /* end of ixSspAccTxFIFOLevelGet */

PUBLIC UINT8
ixSspAccRxFIFOLevelGet (
    void)
{
    /* Disallow this function from running if SSP not initialized */
    IX_SSP_INIT_SUCCESS_CHECK("ixSspAccRxFIFOLevelGet", IX_SSP_FIFO_EMPTY);

    ixSspAccStsStored = IX_OSAL_READ_LONG (ixSspSRAddr);
    /* If the Rx FIFO level is non-zero, the value is the actual level */
    if(IX_SSP_FIFO_FULL_OR_EMPTY !=
        ((((ixSspAccStsStored & IX_SSP_RX_FIFO_LVL_MASK) >>
        IX_SSP_RX_FIFO_LVL_LOC) + 1) & 0xF))
    {
        return (((ixSspAccStsStored & IX_SSP_RX_FIFO_LVL_MASK) >>
            IX_SSP_RX_FIFO_LVL_LOC) + 1);
    }

    /* If the Rx FIFO level is zero, the value can be 0 (empty) or 16 (full)
    depending on the Rx FIFO Not Empty bit */
    if(IX_SSP_RX_FIFO_EMPTY ==
        ((ixSspAccStsStored & IX_SSP_RX_FIFO_NOT_EMPTY_MASK) >>
        IX_SSP_RX_FIFO_NOT_EMPTY_LOC))
    {
        return IX_SSP_FIFO_EMPTY;
    }
    else
    {
        return IX_SSP_FIFO_FULL;
    }
} /* end of ixSspAccRxFIFOLevelGet */

PUBLIC IX_SSP_STATUS
ixSspAccRxFIFOOverrunCheck (
    void)
{
    /* Disallow this function from running if SSP not initialized */
    IX_SSP_INIT_SUCCESS_CHECK("ixSspAccRxFIFOOverrunCheck", IX_SSP_NOT_INIT);

    ixSspAccStsStored = IX_OSAL_READ_LONG (ixSspSRAddr);
    /* Check if an overrun has occurred*/
    if(IX_SSP_OVERRUN_HAS_OCCURRED !=
        ((ixSspAccStsStored & IX_SSP_RX_FIFO_OVERRUN_MASK) >>
        IX_SSP_RX_FIFO_OVERRUN_LOC))
    {
        return IX_SSP_NO_OVERRUN;
    }

    /* Update the overrun stats counter */
    ixSspAccStatsCounters.ixSspOverflowCounter++;
    
    /* Write 1 to clear the overrun bit */
    ixSspAccStsStored = IX_SSP_SET_TO_BE_CLEARED << IX_SSP_RX_FIFO_OVERRUN_LOC; 
    IX_OSAL_WRITE_LONG (ixSspSRAddr, ixSspAccStsStored);

    return IX_SSP_OVERRUN_OCCURRED;
} /* end of ixSspAccRxFIFOOverrunCheck */

/**
 * @ingroup IxSspAcc
 * 
 * @fn ixSspAccInterruptDetected (
    void);
 *
 * @brief The top level Interrupt Service Routine that is called when an SSP
 *          interrupt occurs
 *
 * @param - None 
 *
 * This function is the interrupt service routine that is called when a SSP
 * interrupt occurs. It will determine the source of the interrupt by checking
 * the SSSR and call the appropriate handler - ixRxFIFOOverrunHdlr,
 * ixRxFIFOThsldHdlr, or ixTxFIFOThsldHdlr
 *
 * @return 
 *      - void
 *              
 * @li   Reentrant    : no
 * @li   ISR Callable : yes
 *
 */
PRIVATE void ixSspAccInterruptDetected (
    void)
{
    ixSspAccStsStored = IX_OSAL_READ_LONG (ixSspSRAddr);
    if(IX_SSP_INTERRUPTED == ((ixSspAccStsStored &
        IX_SSP_RX_FIFO_OVERRUN_MASK) >> IX_SSP_RX_FIFO_OVERRUN_LOC))
    {
        /* Increment the overrun counter */
        ixSspAccStatsCounters.ixSspOverflowCounter++;
        
        /* Call the Rx FIFO Overrun handler registered in the IxSspInitVars */
        (*ixRxFIFOOverrunHdlr)();
        
        /* Clear the overrun interrupt */
        ixSspAccStsStored = IX_SSP_SET_TO_BE_CLEARED <<
                            IX_SSP_RX_FIFO_OVERRUN_LOC;
        IX_OSAL_WRITE_LONG (ixSspSRAddr, ixSspAccStsStored);
        return;
    } /* end of rxFIFOOverrun interrupt detected */

    if((IX_SSP_INTERRUPTED ==
        ((ixSspAccStsStored & IX_SSP_RX_FIFO_SVC_REQ_MASK) >>
        IX_SSP_RX_FIFO_SVC_REQ_LOC)) && (NULL != ixRxFIFOThsldHdlr))
    {
        /* Call the Rx FIFO threshold handler registered through the function
            ixSspAccInit or ixSspAccRxFIFOIntEnable */
        (*ixRxFIFOThsldHdlr)();
        return;
    } /* end of rxFIFO interrupt detected */
    
    if((IX_SSP_INTERRUPTED ==
        ((ixSspAccStsStored & IX_SSP_TX_FIFO_SVC_REQ_MASK) >>
        IX_SSP_TX_FIFO_SVC_REQ_LOC)) && (NULL != ixTxFIFOThsldHdlr))
    {
        /* Call the Tx FIFO threshold handler registered through the function
            ixSspAccInit or ixSspAccTxFIFOIntEnable */
        (*ixTxFIFOThsldHdlr)();
        return;
    } /* end of TxFIFO interrupt detected */

    ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR,
        "ixSspAccInterruptDetected(): INVALID STATE REACHED\n", 0,0,0,0,0,0);
    return;
} /* end of ixSspAccInterruptDetected */

#endif /* __ixp46X */