ixperfprofaccxscalepmu.c

有关ARM开发板上的IXP400网络驱动程序的源码以。

                 } /*end of if !IxPerfProfAccXscalePmuIntrStatus */
            }/*end of if-else IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES*/
        }/*end of if-else eventCounting*/
    }/*end of if overflow in clock counter*/

    /* overflow occured in evt counter 1; for evt counting, only occurs when
     * counter is full
     */
    if (overflow & IX_PERFPROF_ACC_XSCALE_PMU_OFLOW_FLAG_PMN0)
    {
        _ixPerfProfAccXscalePmuEventHandler (
            IX_PERFPROF_ACC_XSCALE_PMU_OFLOW_FLAG_PMN0,
            IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR1_ID,
            pcAddr);
    }/*end of else if overflow in evt counter 1*/

    /* overflow occured in evt counter 2; for evt counting, only occurs when
     * counter is full
     */
    if (overflow & IX_PERFPROF_ACC_XSCALE_PMU_OFLOW_FLAG_PMN1)
    {
        _ixPerfProfAccXscalePmuEventHandler (
            IX_PERFPROF_ACC_XSCALE_PMU_OFLOW_FLAG_PMN1,
            IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR2_ID,
            pcAddr);
    }

    /* overflow occured in evt counter 3; for evt counting, only occurs when
     * counter is full
     */
    if (overflow & IX_PERFPROF_ACC_XSCALE_PMU_OFLOW_FLAG_PMN2)
    {
        _ixPerfProfAccXscalePmuEventHandler (
            IX_PERFPROF_ACC_XSCALE_PMU_OFLOW_FLAG_PMN2,
            IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR3_ID,
            pcAddr);
    }/*end of else if overflow in evt counter 3*/

    /* overflow occured in evt counter 4; for evt counting, only occurs when
     * counter is full
     */
    if (overflow & IX_PERFPROF_ACC_XSCALE_PMU_OFLOW_FLAG_PMN3)
    {
        _ixPerfProfAccXscalePmuEventHandler (
            IX_PERFPROF_ACC_XSCALE_PMU_OFLOW_FLAG_PMN3,
            IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR4_ID,
            pcAddr);
    }/*end of else if overflow in evt counter 4*/

    /* Clear all bits in overflow flag register*/
    _ixPerfProfAccXscalePmuOverFlowWrite(
        IX_PERFPROF_ACC_XSCALE_PMU_OFLOW_FLAG_ALL);
}/*end of ixPerfProfAccXscalePmuIntrHandler()*/

void
ixPerfProfAccXscalePmuIntrConnect(void)
{
    /*Call intconnect() to connect interrupt handler*/
    ixOsalIrqBind(IX_OSAL_IXP400_XSCALE_PMU_IRQ_LVL,
		  (IxOsalVoidFnVoidPtr)ixPerfProfAccXscalePmuIntrHandler,
		  NULL);
}

void
ixPerfProfAccXscalePmuIntrEnable(BOOL clkCtr)
{
    UINT32 intrEnableRegBit = 0;    /*value to enter when enabling pmu interrupt
                                     *register
                                     */

    /*merely write to pmu interrupt enable register, nothing else; set the
     *appropriate bits in the PMU Interrupt Enable Register to enable
     *the interrupts for each clock or event counter
     */
    switch (numberEvents)
    {
        case 4: /*event counters 1,2,3,4 being monitored*/
            /*enable bits 1 to 4*/
            intrEnableRegBit |= IX_PERFPROF_ACC_XSCALE_PMU_OFLOW_FLAG_PMN3;

        case 3: /*event counters 1,2,3 being monitored*/
            /*enable bits 1,2 and 3*/
            intrEnableRegBit |= IX_PERFPROF_ACC_XSCALE_PMU_OFLOW_FLAG_PMN2;

        case 2: /*event counters 1,2 being monitored*/
            /*enable bits 1 and 2*/
            intrEnableRegBit |= IX_PERFPROF_ACC_XSCALE_PMU_OFLOW_FLAG_PMN1;

        case 1: /*only event counter 1 is being monitored; enable bit 1*/
            intrEnableRegBit |= IX_PERFPROF_ACC_XSCALE_PMU_OFLOW_FLAG_PMN0;
            break;

        default:
            break;
    }/*end of switch numberEvents*/

    if (clkCtr) /*for clock counting only or any event counting, need to enable
                 *clk ctr bit as well
                 */
    {
        intrEnableRegBit |= IX_PERFPROF_ACC_XSCALE_PMU_OFLOW_FLAG_CCNT;
    } /*end of if clkCtr*/

    /*write value of the interrupt enable register bit*/
    _ixPerfProfAccXscalePmuIntenWrite (intrEnableRegBit);
}/*end of ixPerfProfAccXscalePmuIntrEnable()*/

void
ixPerfProfAccXscalePmuBspIntrEnable(void)
{
    UINT32 *pIntrEnableRegAdd;     /*pointer to interrupt enable register*/

    /*enable xscale interrupt in the interrupt controller register*/
    pIntrEnableRegAdd =
        (UINT32 *)IX_PERFPROF_ACC_XSCALE_PMU_INTR_ENABLE_REG_ADD;

    /*set bit 18 to allow the XScale core to enable the interrupts*/
    *pIntrEnableRegAdd =
        ((*pIntrEnableRegAdd) |
         IX_PERFPROF_ACC_XSCALE_PMU_XSCALE_INTERRUPT_ENABLE_BIT);
}/*end of ixPerfProfAccXscalePmuBspIntrEnable()*/

void
ixPerfProfAccXscalePmuEventSelect (
    IxPerfProfAccXscalePmuEvent pmuEvent1,
    IxPerfProfAccXscalePmuEvent pmuEvent2,
    IxPerfProfAccXscalePmuEvent pmuEvent3,
    IxPerfProfAccXscalePmuEvent pmuEvent4)
{
    UINT32 evtSelRegVal = 0;    /*value to be written into each event counter*/

    switch (numberEvents) /*numberEvents is passed in by client when calling
                           *the start function for event counting/sampling;
                           *the event select register is 32bits, with every 8
                           *bits representing event counters 1-4; the bits
                           *corresponding to each event selected are written
                           *into this register
                           */
    {
        /*only 1 event specified; write value into counter 1
         *counter 1 is the first 8 bits in the event select register
         */
        case 1:
            evtSelRegVal = (pmuEvent1 | IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR1);
            break;

        /*2 events specified; write value into counters 1,2
         *counter 2 is bits 8-15 in the event select register
         */
        case 2:
            evtSelRegVal =
                ((pmuEvent2 <<
                  IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR2_BITS_TO_SHIFT) |
                 pmuEvent1 |
                 IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR2);
            break;

        /*3 events specified; write value into counters 1,2,3
         *counter 3 is bits 16-23 in the event select register
         */
        case 3:
            evtSelRegVal =
                ((pmuEvent3 <<
                  IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR3_BITS_TO_SHIFT) |
                 (pmuEvent2 <<
                  IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR2_BITS_TO_SHIFT) |
                 pmuEvent1 |
                 IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR3);
            break;

        /*4 events specified; write value into counters 1,2,3,4
         *counter 4 is bits 24-31 in the event select register
         */
        case 4:
            evtSelRegVal =
                ((pmuEvent4 <<
                  IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR4_BITS_TO_SHIFT) |
                 (pmuEvent3 <<
                  IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR3_BITS_TO_SHIFT) |
                 (pmuEvent2 <<
                  IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR2_BITS_TO_SHIFT) |
                 pmuEvent1);
            break;

        default:
            break;
    }/*end of switch (numnerEvents)*/

    /*write the value into the Event Select Register*/
    _ixPerfProfAccXscalePmuEvtSelectWrite(evtSelRegVal);
}/*end of ixPerfProfAccXscalePmuEventSelect()*/

void
ixPerfProfAccXscalePmuCtrEnableReset (
    BOOL clkCntDiv,
    BOOL enableCtrs,
    BOOL resetClkCtr,
    BOOL resetEvtCtr)
{
    UINT32 perfMtrCtrlRegBit = 0;   /*value to write to PMNC register*/

    if ( TRUE == clkCntDiv) /*clk counter divider is enabled*/
    {
        perfMtrCtrlRegBit = IX_PERFPROF_ACC_XSCALE_PMU_PMNC_DIVIDER;
    }
    if (enableCtrs) /*if need to enable counters*/
    {
        perfMtrCtrlRegBit = (perfMtrCtrlRegBit |
                             IX_PERFPROF_ACC_XSCALE_PMU_PMNC_ENABLE);
    }
    else
    {
        perfMtrCtrlRegBit = (perfMtrCtrlRegBit |
                             IX_PERFPROF_ACC_XSCALE_PMU_PMNC_DISABLE);
    }/*end of if enableCtrs*/
    if (resetClkCtr)
    {
        perfMtrCtrlRegBit = (perfMtrCtrlRegBit |
                             IX_PERFPROF_ACC_XSCALE_PMU_PMNC_RESET_CLK_CTR);
    }/*end of if resetClkCtr*/
    if (resetEvtCtr)
    {
        perfMtrCtrlRegBit = (perfMtrCtrlRegBit |
                             IX_PERFPROF_ACC_XSCALE_PMU_PMNC_RESET_EVT_CTR);
    } /*end of resetEvtCtr*/

    /*write the appropriate value to the PMNC reg*/
    _ixPerfProfAccXscalePmuPmncWrite(perfMtrCtrlRegBit);
}/*end of ixPerfProfAccXscalePmuCtrEnableReset()*/

IxPerfProfAccStatus
ixPerfProfAccXscalePmuEvtCtrInit (void)
{
    BOOL checkNum = TRUE;   /*determines if num passed into
                             *_ixPerfProfAccXscalePmuPmnWrite is valid
                             */
    if ((0 == numberEvents ) ||
       (IX_PERFPROF_ACC_XSCALE_PMU_MAX_EVENTS <
        numberEvents ))
    {
        return IX_PERFPROF_ACC_STATUS_FAIL;
    }
    switch (numberEvents)
    {
        case 4:
            _ixPerfProfAccXscalePmuPmnWrite(
                IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR4_ID,
                ctrBase[IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR4_ID],
                &checkNum);
            if (FALSE == checkNum)/*num passed into
                                   *_ixPerfProfAccXscalePmuPmnWrite is
                                   *greater than max allowed event counters
                                   */
            {
                return IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID;
            }

        case 3:
            _ixPerfProfAccXscalePmuPmnWrite(
                IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR3_ID,
                ctrBase[IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR3_ID],
                &checkNum);
            if (FALSE == checkNum)/*num passed into
                                   *_ixPerfProfAccXscalePmuPmnWrite is
                                   *greater than max allowed event counters
                                   */
            {
                return IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID;
            }

        case 2:
            _ixPerfProfAccXscalePmuPmnWrite(
                IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR2_ID,
                ctrBase[IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR2_ID],
                &checkNum);
            if (FALSE == checkNum)/*num passed into
                                   *_ixPerfProfAccXscalePmuPmnWrite is
                                   *greater than max allowed event counters
                                   */
            {
                return IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID;
            }

        case 1:
            _ixPerfProfAccXscalePmuPmnWrite(
                IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR1_ID,
                ctrBase[IX_PERFPROF_ACC_XSCALE_PMU_EVT_CTR1_ID],
                &checkNum);
            if (FALSE == checkNum)/*num passed into
                                   *_ixPerfProfAccXscalePmuPmnWrite is
                                   *greater than max allowed event counters
                                   */
            {
                return IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID;
            }
            break;

        default:
            break;

    }/*end of switch (numberEvents)*/
    return IX_PERFPROF_ACC_STATUS_SUCCESS;
}/*end of ixPerfProfAccXscalePmuEvtCtrInit()*/

void
ixPerfProfAccXscalePmuIntrDisable (void)
{
    /*write to the PMNC to disable all clock and event counters*/
    _ixPerfProfAccXscalePmuPmncWrite(IX_PERFPROF_ACC_XSCALE_PMU_PMNC_DISABLE);

    /*disable all counter interrupts in interrupt enable register*/
    _ixPerfProfAccXscalePmuIntenWrite(
        IX_PERFPROF_ACC_XSCALE_PMU_INTR_DISABLE_ALL);

    /*disable xscale interrupt in the interrupt controller register*/
    ixOsalIrqUnbind(IX_PERFPROF_ACC_XSCALE_PMU_BSP_INTR_BIT);
}   /* end of ixPerfProfAccXscalePmuIntrDisable() */

void
ixPerfProfAccXscalePmuClkCntGet (IxPerfProfAccXscalePmuEvtCnt *clkCount)
{
    UINT32 currentCnt = _ixPerfProfAccXscalePmuCcntRead();  /*get current value
                                                             *of clk counter
                                                             */

    if (!eventCounting)  /*for time-based sampling*/
    {
        if (IxPerfProfAccXscalePmuIntrStatus[
                IX_PERFPROF_ACC_XSCALE_PMU_CLK_CTR_ID] == TRUE)
        {
            /*logs a warning*/
            IX_PERFPROF_ACC_LOG(
		IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT,
                "*** Warning: Profiling table is full!\n\n",
                0,0, 0, 0, 0, 0);
        } /*end of if IxPerfProfAccXscalePmuIntrStatus*/
    }/*end of if !eventCounting*/

    /*assign value of end clock count*/
    clkCount->lower32BitsEventCount =
        currentCnt -
        ctrBase[IX_PERFPROF_ACC_XSCALE_PMU_CLK_CTR_ID];

    /*assign value of number of overflows for the clock counter*/
    clkCount->upper32BitsEventCount =
        ctrSamples[IX_PERFPROF_ACC_XSCALE_PMU_CLK_CTR_ID];
} /*end of ixPerfProfAccXscalePmuClkCntGet()*/

IxPerfProfAccStatus
ixPerfProfAccXscalePmuEvtCntGet (IxPerfProfAccXscalePmuEvtCnt *eventCount)
{
    UINT32 i;
    IxPerfProfAccStatus status = IX_PERFPROF_ACC_STATUS_SUCCESS;
    UINT32 currentCnt[IX_PERFPROF_ACC_XSCALE_PMU_MAX_EVENTS];/*local to this
                                                              *function
                                                              */
    BOOL checkNum = TRUE;
    for (i=0; i<IX_PERFPROF_ACC_XSCALE_PMU_MAX_EVENTS; i++)
    {
        currentCnt[i] = _ixPerfProfAccXscalePmuPmnRead(i, &checkNum);
        /*num events passed in to _ixPerfProfAccXscalePmuPmnRead is invalid*/
        if (FALSE == checkNum)
        {
            status = IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID;
            return status;
        } /*end of if FALSE==checkNum*/
    }/*end of for IX_PERFPROF_ACC_XSCALE_PMU_MAX_EVENTS loop*/

    for (i=0; i < numberEvents; i++)
    {
        /*results overflow use next 32bit counter to store overflow for event
         *counting
         */
        if(((eventCounting) &&