ixperfprofaccxscalepmu.c

有关ARM开发板上的IXP400网络驱动程序的源码以。

/**
 * @file IxPerfProfAccXscalePmu.c
 *
 * @date April-09-2003
 *
 * @brief  Source file for the Xscale PMU public APIs and internal functions
 *
 *
 * Design Notes:
 *
 * 
 * @par
 * IXP400 SW Release version 2.1
 * 
 * -- Copyright Notice --
 * 
 * @par
 * Copyright (c) 2001-2005, Intel Corporation.
 * All rights reserved.
 * 
 * @par
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 
 * 
 * @par
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * 
 * @par
 * -- End of Copyright Notice --
 */

/*
 * Put the system defined include files required.
 */

#ifdef __vxworks
#include <symLib.h>
#include <sysSymTbl.h>
#include <stdio.h>
#elif defined (__linux)
#include <linux/module.h>
#endif

/*
 * Put the user defined include files required.
 */
#include "IxOsal.h"
#include "IxPerfProfAcc.h"
#include "IxFeatureCtrl.h"
#include "IxPerfProfAccXscalePmu_p.h"
#include "IxPerfProfAcc_p.h"

/*
 * #defines and macros used in this file.
 */

/* Maximum value for 32-bit counters*/
#define IX_PERFPROF_ACC_XSCALE_PMU_MAX_COUNTER_VALUE 0xffffffff

/* Num bits to shift in order to multiply by 8*/
#define IX_PERFPROF_ACC_XSCALE_PMU_SHIFT_TO_MULT_8 3

/* Define string size to be used to display symbol name */
#define IX_PERFPROF_ACC_XSCALE_PMU_SYMBOL_SIZE 1024

/*
 * Variable declarations global to this file only.  Externs are followed by
 * static variables
 */
#ifdef __vxworks
IMPORT UINT32 (*vxIrqIntStackBase)[]; /*base of interrupt stack*/
#endif /*ifdef vxworks*/

#ifdef __linux
extern UINT32 ixOsalLinuxInterruptedPc;
#endif

/* base value to be written to counters (overflow rate in cases of sampling)
 * this is an array of 5 elements, representing all the counters
 */
static UINT32 ctrBase[IX_PERFPROF_ACC_XSCALE_PMU_MAX_COUNTERS];
static UINT32 numberEvents = 0;    /*number of events to be monitored*/
static BOOL eventCounting = FALSE;  /*TRUE if event counting is on */

/* number of samples (overflows) for each counter; this is an array of 5
 * elements, representing all the counters
 */
static UINT32 ctrSamples[IX_PERFPROF_ACC_XSCALE_PMU_MAX_COUNTERS];

/* TRUE if buffer results full; FALSE if counter overflow */
static BOOL IxPerfProfAccXscalePmuIntrStatus [
    IX_PERFPROF_ACC_XSCALE_PMU_MAX_COUNTERS];

/*arrays to store pc addresses for each interrupt*/
static UINT32 clkCtrArray[IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES];
static UINT32 evtCtr1Array[IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES];
static UINT32 evtCtr2Array[IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES];
static UINT32 evtCtr3Array[IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES];
static UINT32 evtCtr4Array[IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES];
static UINT32  sumLen; /*number of occurrences of profile*/

static BOOL eventCountStarted = FALSE;  /*is TRUE if event counting has been
                                         *started; FALSE otherwise
                                         */
static BOOL timeSampStarted = FALSE;    /*is TRUE if time sampling has been
                                         *started; FALSE otherwise
                                         */
static BOOL eventSampStarted = FALSE;   /*is TRUE if event sampling has been
                                         *started; FALSE otherwise
                                         */

#ifdef __linux
/* Xscale PMU time sampling profile results used for linux file writing*/
static IxPerfProfAccXscalePmuSamplePcProfile  
             timeSampProfile[IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES];
static IxPerfProfAccXscalePmuSamplePcProfile 
             eventSampProfile1[IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES];
static IxPerfProfAccXscalePmuSamplePcProfile 
             eventSampProfile2[IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES];
static IxPerfProfAccXscalePmuSamplePcProfile 
             eventSampProfile3[IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES];
static IxPerfProfAccXscalePmuSamplePcProfile 
             eventSampProfile4[IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES];
#endif

/*
 * Function definition.
 */

#ifndef _DIAB_TOOL
INLINE UINT32
_ixPerfProfAccXscalePmuOverFlowRead(void)
{
    register UINT32 _value_;

    /*move to overflow flag status register from coprocessor 14 and store in
     *value
     */
    __asm volatile("mrc\tp14, 0, %0, c5, c1, 0" : "=r" (_value_));
    return _value_ & 0x1f; /*only set first 5 bits in the status register*/
}

INLINE void
_ixPerfProfAccXscalePmuOverFlowWrite(UINT32 value)
{
    /*move value to coprocessor 14 from overflow flag status register*/
    __asm("mcr\tp14, 0, %0, c5, c1, 0" : : "r" (value));
}

INLINE UINT32
_ixPerfProfAccXscalePmuCcntRead(void)
{
    register UINT32 _value_;

    /*move to ccnt (clk counter) register from coprocessor 14 and store in value
     */
    __asm volatile("mrc\tp14, 0, %0, c1, c1, 0" : "=r" (_value_));
    return _value_;
}

INLINE void
_ixPerfProfAccXscalePmuCcntWrite(UINT32 value)
{
    /*move value to coprocessor 14 from ccnt (clk counter) register*/
    __asm("mcr\tp14, 0, %0, c1, c1, 0" : : "r" (value));
}

INLINE unsigned
_ixPerfProfAccXscalePmuIntenRead(void)
{
    register UINT32 _value_;

    /*move to interrupt enable register from coprocessor 14 and store in value*/
    __asm volatile("mrc\tp14, 0, %0, c4, c1, 0" : "=r" (_value_));
    return _value_ & 0x1f; /*mask return value to ensure only first 5 bits in
                            *the register are set
                            */
}

INLINE void
_ixPerfProfAccXscalePmuIntenWrite(UINT32 value)
{
    /*move value to coprocessor 14 from interrupt enable register*/
    __asm("mcr\tp14, 0, %0, c4, c1, 0" : : "r" (value));
}

INLINE UINT32
_ixPerfProfAccXscalePmuPmncRead(void)
{
    register UINT32 _value_;

    /*move to performance monitor control register from coprocessor 14 and store
     *in value
     */
    __asm volatile("mrc\tp14, 0, %0, c0, c1, 0" : "=r" (_value_));
    return _value_ & 0xf;    /*mask return value to ensure only first 4 bits in
                              *the register are set
                              */
}

INLINE void
_ixPerfProfAccXscalePmuPmncWrite(UINT32 value)
{
    /*move value to coprocessor 14 from performance monitor control register*/
    __asm("mcr\tp14, 0, %0, c0, c1, 0" : : "r" (value));
}

INLINE void
_ixPerfProfAccXscalePmuEvtSelectWrite(UINT32 value)
{
    /*move to event select register from coprocessor 14 and store
     *in value
     */
    __asm("mcr\tp14, 0, %0, c8, c1, 0" : : "r" (value));
}

INLINE UINT32
_ixPerfProfAccXscalePmuEvtSelectRead(void)
{
    /*move to event select register from coprocessor 14 and store
     *in value
     */
    register UINT32 value = 0;
    __asm("mrc\tp14, 0, %0, c8, c1, 0" : : "r" (value));
    return (value);
}

INLINE UINT32
_ixPerfProfAccXscalePmuPmnRead(UINT32 num, BOOL *check)
{
    register UINT32 _value_ = 0;
    if (IX_PERFPROF_ACC_XSCALE_PMU_MAX_EVENTS < num) /*num passed in exceeds
                                                      *maximum counters allowed
                                                      */
    {
        *check = FALSE;
    }
    switch (num)/*move value to coprocessor 14 from event counter registers*/
    {
        case 0: /*read value of event counter 1 only*/
            __asm volatile("mrc\tp14, 0, %0, c0, c2, 0" : "=r" (_value_));
            break;

        case 1: /*read value of event counter 2 only*/
            __asm volatile("mrc\tp14, 0, %0, c1, c2, 0" : "=r" (_value_));
            break;

        case 2: /*read value of event counter 3 only*/
            __asm volatile("mrc\tp14, 0, %0, c2, c2, 0" : "=r" (_value_));
            break;

        case 3: /*read value of event counter 4 only*/
            __asm volatile("mrc\tp14, 0, %0, c3, c2, 0" : "=r" (_value_));
            break;

        default:
            break;
    }
    return _value_;
}

INLINE void
_ixPerfProfAccXscalePmuPmnWrite(UINT32 num, UINT32 value, BOOL *check)
{
    /*set value of *check to FALSE if num passed in is greater than maximum
     *counters allowed
     */
    if(IX_PERFPROF_ACC_XSCALE_PMU_MAX_EVENTS<num)
    {
        *check = FALSE;
    } /*end of if IX_PERFPROF_ACC_XSCALE_PMU_MAX_EVENTS*/

    switch (num)/*move to event counter registers from coprocessor 14 and store
                 *in value
                 */
    {
        case 0:   /*write value to event counter 1 only*/
            __asm("mcr\tp14, 0, %0, c0, c2, 0" : : "r" (value));
            break;

        case 1:   /*write value to event counter 2 only*/
            __asm("mcr\tp14, 0, %0, c1, c2, 0" : : "r" (value));
            break;

        case 2:   /*write value to event counter 3 only*/
            __asm("mcr\tp14, 0, %0, c2, c2, 0" : : "r" (value));
            break;

        case 3:   /*write value to event counter 4 only*/
            __asm("mcr\tp14, 0, %0, c3, c2, 0" : : "r" (value));
            break;

        default:
            break;
    } /*end of switch (num )*/
} /*end of _ixPerfProfAccXscalePmuPmnWrite()*/

#else /* _DIAB_TOOL defined */
__asm volatile UINT32
_ixPerfProfAccXscalePmuOverFlowRead(void)
{
! "r0"
    /*move to overflow flag status register from coprocessor 14 and store in
     *value
     */
    mrc\tp14, 0, r0, c5, c1, 0;
    and	r0, r0, #31; /*only set first 5 bits in the status register*/
    ;/* return value is returned through register R0 */
}

__asm volatile void
_ixPerfProfAccXscalePmuOverFlowWrite(UINT32 value)
{
%reg value
    /*move value to coprocessor 14 from overflow flag status register*/
    mcr\tp14, 0, value, c5, c1, 0;
}

__asm volatile UINT32
_ixPerfProfAccXscalePmuCcntRead(void)
{
! "r0"
    /*move to ccnt (clk counter) register from coprocessor 14 and store in value
     */
    mrc\tp14, 0, r0, c1, c1, 0;
    ;/* return value is returned through register R0 */
}

__asm volatile void
_ixPerfProfAccXscalePmuCcntWrite(UINT32 value)
{
% reg value
    /*move value to coprocessor 14 from ccnt (clk counter) register*/
    mcr\tp14, 0, value, c1, c1, 0;
}

__asm volatile unsigned
_ixPerfProfAccXscalePmuIntenRead(void)
{
! "r0"

    /*move to interrupt enable register from coprocessor 14 and store in value*/
    mrc\tp14, 0, r0, c4, c1, 0;
    and	r0, r0, #31; /*mask return value to ensure only first 5 bits in
                            *the register are set
                            */
    ;/* return value is returned through register R0 */
}

__asm volatile void
_ixPerfProfAccXscalePmuIntenWrite(UINT32 value)
{
% reg value