ixperfprofaccbuspmu_p.h

有关ARM开发板上的IXP400网络驱动程序的源码以。

/**
 * @file IxPerfProfAccBusPmu_p.h
 *
 * @date April 9 2003
 *
 * @brief Private header file for the  BUS PMU portion of the IxPerfProfAcc
 * software component
 *
 *
 * Design Notes:
 *
 * 
 * @par
 * IXP400 SW Release version 2.1
 * 
 * -- Copyright Notice --
 * 
 * @par
 * Copyright (c) 2001-2005, Intel Corporation.
 * All rights reserved.
 * 
 * @par
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 
 * 
 * @par
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * 
 * @par
 * -- End of Copyright Notice --
 */

#ifndef IXPERFPROFACCBUSPMU_P_H
#define IXPERFPROFACCBUSPMU_P_H

#include "IxOsal.h"

#ifdef __vxworks
/* Variable to be used in Macros below indicating the virtually mapped addresses */
UINT32 esrVirtualAddress;
UINT32 srVirtualAddress;
UINT32 pmsrVirtualAddress;
UINT32 pecVirtualAddress;
#endif /* __vxworks */

/* PMU registers memory mapping */

#define ESR_MODE_BITS_OFFSET            2 /* Offsets the mode bits in the Event Status 
                                             Register */
#define NUM_OF_PEC_BITS                 3 /* Number od bits to select an event for a
                                             particular PEC */
#define ESR_MODE_BITS_MASK              0xfffffffc /* Mask out the mode bits in the ESR */
#define STATUS_REGISTER_RESET           0xffffffff /* Value to write to the  status register 
                                                      with to reset the register */
#define PEC_REGISTER_27BIT_MASK         0x7ffffff  /* Value to mask the PEC and obtain the
                                                      counter value */
#define PEC_REGISTER_OFFSET             0x4        /* Value to offset before accessing next
                                                      PEC register address */
#define PEC_INCREMENT                   1          /* Increments the PEC value when calling 
                                                      from function */
#define ESR_MODE_MASK                   0x3        /* Mask for the mode field in the esr */
#define STATUS_REGISTER_BIT1_MASK       0x1

/* Registers off set value from base address */
#define STATUS_REGISTER_ADDR_OFFSET     0x4
#define PEC1_ADDR_OFFSET                0x8
#define PEC2_ADDR_OFFSET                0xc
#define PEC3_ADDR_OFFSET                0x10
#define PEC4_ADDR_OFFSET                0x14
#define PEC5_ADDR_OFFSET                0x18
#define PEC6_ADDR_OFFSET                0x1c
#define PEC7_ADDR_OFFSET                0x20
#define PMSR_ADDR_OFFSET                0x24
 
/* Addresses for all the available registers. Event Status Register, Status register
   Programmable Event Counter, and Previous Master Slave Register */
#ifdef __vxworks
#define IX_PERFPROF_IXP400_PMU_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE + 0x00002000)
#elif defined(__linux)
#define IX_PERFPROF_IXP400_PMU_BASE (IX_OSAL_IXP400_PERIPHERAL_VIRT_BASE + 0x2000)
#endif

#define PMU_ESR               (IX_PERFPROF_IXP400_PMU_BASE)
#define PMU_SR                (IX_PERFPROF_IXP400_PMU_BASE+STATUS_REGISTER_ADDR_OFFSET)
#define PMU_PEC1              (IX_PERFPROF_IXP400_PMU_BASE+PEC1_ADDR_OFFSET)
#define PMU_PEC2              (IX_PERFPROF_IXP400_PMU_BASE+PEC2_ADDR_OFFSET)
#define PMU_PEC3              (IX_PERFPROF_IXP400_PMU_BASE+PEC3_ADDR_OFFSET)
#define PMU_PEC4              (IX_PERFPROF_IXP400_PMU_BASE+PEC4_ADDR_OFFSET)
#define PMU_PEC5              (IX_PERFPROF_IXP400_PMU_BASE+PEC5_ADDR_OFFSET)
#define PMU_PEC6              (IX_PERFPROF_IXP400_PMU_BASE+PEC6_ADDR_OFFSET)
#define PMU_PEC7              (IX_PERFPROF_IXP400_PMU_BASE+PEC7_ADDR_OFFSET)
#define PMU_PMSR              (IX_PERFPROF_IXP400_PMU_BASE+PMSR_ADDR_OFFSET)

#ifdef __vxworks
/* Macro to write selected value to the Event Status Register */
#define SET_PMU_ESR(value)    (IX_OSAL_WRITE_LONG(esrVirtualAddress, value))
/* Macro to get ESR value */
#define GET_PMU_ESR           (IX_OSAL_READ_LONG(esrVirtualAddress))
/* Macro to reset status register */
#define SR_RESET()            (IX_OSAL_WRITE_LONG(srVirtualAddress,STATUS_REGISTER_RESET))
/* Macro to read from status register */
#define GET_SR()              (IX_OSAL_READ_LONG(srVirtualAddress))
/* macro to select PEC and read its value */
#define PMU_CNT_ADDR(pec)     (IX_PERFPROF_IXP400_PMU_BASE + PEC_REGISTER_OFFSET + (PEC_REGISTER_OFFSET * (pec)))
#define PMU_CNT_PMSR()        (IX_OSAL_READ_LONG(pmsrVirtualAddress))
#define PMU_CNT_GET()         (IX_OSAL_READ_LONG(pecVirtualAddress)& PEC_REGISTER_27BIT_MASK)

#elif defined(__linux)
/* Macro to write selected value to the Event Status Register */
#define SET_PMU_ESR(value)    (IX_OSAL_WRITE_LONG(PMU_ESR, value))
/* Macro to get ESR value */
#define GET_PMU_ESR           (IX_OSAL_READ_LONG(PMU_ESR))
/* Macro to reset status register */
#define SR_RESET()            (IX_OSAL_WRITE_LONG(PMU_SR, STATUS_REGISTER_RESET))
/* Macro to read from status register */
#define GET_SR()              (IX_OSAL_READ_LONG(PMU_SR))
/* macro to select PEC and read its value */
#define PMU_CNT_ADDR(pec)     (IX_PERFPROF_IXP400_PMU_BASE + PEC_REGISTER_OFFSET + (PEC_REGISTER_OFFSET * (pec)))
#define PMU_CNT_PMSR()        (IX_OSAL_READ_LONG(PMU_PMSR))
#define PMU_CNT_GET(pec)      (IX_OSAL_READ_LONG(PMU_CNT_ADDR(pec))& PEC_REGISTER_27BIT_MASK)

#endif /* __vxworks */

/* Macros for register manipulation */
/* Value by which to offset the ESR in order for a particular PEC to be selected. */ 
#define PEC_SELECT_VALUE(counter)       (ESR_MODE_BITS_OFFSET + (NUM_OF_PEC_BITS * (IX_PERFPROF_ACC_BUS_PMU_MAX_PECS - (counter + PEC_INCREMENT))))
/* Macro to select event for a particular PEC */
#define SET_PMU_PEC(value,pec,event)    (value) = (value) | ((event) << PEC_SELECT_VALUE(pec))
/* Macro set the mode required */
#define SET_PMU_MODE(value,mode)        (value) = ((value) & ESR_MODE_BITS_MASK) | (mode)
/* Macro to reset event status register */ 
#define ESR_RESET()                     (SET_PMU_ESR(0)) 
#define PMU_HALT()                      (SET_PMU_MODE((GET_PMU_ESR), IX_PERFPROF_ACC_BUS_PMU_MODE_HALT))


/* Event for all counters. Memory mapped values */
#define PEC1_NORTH_NPEA_GRANT           0x0
#define PEC1_NORTH_NPEB_GRANT           0x1
#define PEC1_NORTH_NPEC_GRANT           0x2
#define PEC1_NORTH_BUS_IDLE             0x4
#define PEC1_NORTH_NPEA_REQ             0x5
#define PEC1_NORTH_NPEB_REQ             0x6
#define PEC1_NORTH_NPEC_REQ             0x7

#define PEC1_SOUTH_GSKT_GRANT           0x0
#define PEC1_SOUTH_ABB_GRANT            0x1
#define PEC1_SOUTH_PCI_GRANT            0x2
#define PEC1_SOUTH_APB_GRANT            0x3
#define PEC1_SOUTH_GSKT_REQ             0x4
#define PEC1_SOUTH_ABB_REQ              0x5
#define PEC1_SOUTH_PCI_REQ              0x6
#define PEC1_SOUTH_APB_REQ              0x7

#define PEC1_SDR_0_HIT                  0x0
#define PEC1_SDR_1_HIT                  0x1
#define PEC1_SDR_2_HIT                  0x2
#define PEC1_SDR_3_HIT                  0x3
#define PEC1_SDR_4_MISS                 0x4
#define PEC1_SDR_5_MISS                 0x5
#define PEC1_SDR_6_MISS                 0x6
#define PEC1_SDR_7_MISS                 0x7

#define PEC2_NORTH_NPEA_XFER            0x0
#define PEC2_NORTH_NPEB_XFER            0x1
#define PEC2_NORTH_NPEC_XFER            0x2
#define PEC2_NORTH_BUS_WRITE            0x4
#define PEC2_NORTH_NPEA_OWN             0x5
#define PEC2_NORTH_NPEB_OWN             0x6
#define PEC2_NORTH_NPEC_OWN             0x7

#define PEC2_SOUTH_GSKT_XFER            0x0
#define PEC2_SOUTH_ABB_XFER             0x1
#define PEC2_SOUTH_PCI_XFER             0x2
#define PEC2_SOUTH_APB_XFER             0x3
#define PEC2_SOUTH_GSKT_OWN             0x4
#define PEC2_SOUTH_ABB_OWN              0x5
#define PEC2_SOUTH_PCI_OWN              0x6