📄 ixperfprofaccbuspmu.c
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(modeEvents.counterEvent1 > IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_7_MISS_SELECT)) { return IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC1_ERROR; } /* Event select for PEC1 */ SET_PMU_PEC(esrValue,PEC1,ixPerfProfAccBusPmuEventMap[modeEvents.counterEvent1]); /* Check if PEC2 selection is within range for Sdram Mode */ if((modeEvents.counterEvent2 < IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_1_HIT_SELECT)|| (modeEvents.counterEvent2 > IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_0_MISS_SELECT)) { return IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC2_ERROR; } /* Event select for PEC2 */ SET_PMU_PEC(esrValue,PEC2,ixPerfProfAccBusPmuEventMap[modeEvents.counterEvent2]); /* Check if PEC3 selection is within range for Sdram Mode */ if((modeEvents.counterEvent3 < IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_2_HIT_SELECT)|| (modeEvents.counterEvent3 > IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_1_MISS_SELECT)) { return IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC3_ERROR; } /* Event select for PEC3 */ SET_PMU_PEC(esrValue,PEC3,ixPerfProfAccBusPmuEventMap[modeEvents.counterEvent3]); /* Check if PEC4 selection is within range for Sdram Mode */ if((modeEvents.counterEvent4 < IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_3_HIT_SELECT)|| (modeEvents.counterEvent4 > IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_2_MISS_SELECT)) { return IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC4_ERROR; } /* Event select for PEC4 */ SET_PMU_PEC(esrValue,PEC4,ixPerfProfAccBusPmuEventMap[modeEvents.counterEvent4]); /* Check if PEC5 selection is within range for Sdram Mode */ if((modeEvents.counterEvent5 < IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_4_HIT_SELECT)|| (modeEvents.counterEvent5 > IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_3_MISS_SELECT)) { return IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC5_ERROR; } /* Event select for PEC5 */ SET_PMU_PEC(esrValue,PEC5,ixPerfProfAccBusPmuEventMap[modeEvents.counterEvent5]); /* Check if PEC6 selection is within range for Sdram Mode */ if((modeEvents.counterEvent6 < IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_5_HIT_SELECT)|| (modeEvents.counterEvent6 > IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_4_MISS_SELECT)) { return IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC6_ERROR; } /* Event select for PEC6 */ SET_PMU_PEC(esrValue,PEC6,ixPerfProfAccBusPmuEventMap[modeEvents.counterEvent6]); /* Check if PEC7 selection is within range for Sdram Mode */ if(modeEvents.counterEvent7 != IX_PERFPROF_ACC_BUS_PMU_PEC7_CYCLE_COUNT_SELECT) { return IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC7_ERROR; } /* Event select for PEC7 */ SET_PMU_PEC(esrValue,PEC7,ixPerfProfAccBusPmuEventMap[modeEvents.counterEvent7]); SET_PMU_MODE(esrValue, IX_PERFPROF_ACC_BUS_PMU_MODE_SDRAM); SET_PMU_ESR(esrValue); return IX_PERFPROF_ACC_STATUS_SUCCESS;} /* end of ixPerfProfAccBusPmuSdramCheckAndSelect () *//* Function to setup events for each counter based on the mode */IxPerfProfAccStatusixPerfProfAccBusPmuSetup (IxPerfProfAccBusPmuModeEvents modeEvents){ ESR_RESET(); /* Reset overflow bits in Status Register. */ /* Set the register values for north mode based on parameters input */ if (modeEvents.counterMode == IX_PERFPROF_ACC_BUS_PMU_MODE_NORTH) { return (ixPerfProfAccBusPmuNorthCheckAndSelect(modeEvents)); } /* Set the register values for South mode based on parameters input */ else if (modeEvents.counterMode == IX_PERFPROF_ACC_BUS_PMU_MODE_SOUTH) { return (ixPerfProfAccBusPmuSouthCheckAndSelect(modeEvents)); } /* Set the register values for Sdram mode based on parameters input */ else if (modeEvents.counterMode == IX_PERFPROF_ACC_BUS_PMU_MODE_SDRAM) { return (ixPerfProfAccBusPmuSdramCheckAndSelect(modeEvents)); } /* End if(modeEvents.counterMode == IX_PERFPROF_ACC_BUS_PMU_MODE_SDRAM)*/ return IX_PERFPROF_ACC_STATUS_BUS_PMU_MODE_ERROR;} /* End of function ixPerfProfAccBusPmuSetup*//* Function stops all collection of data */PUBLIC IxPerfProfAccStatusixPerfProfAccBusPmuStop (void){ UINT32 esrValue; if (FALSE == startFlag) { return IX_PERFPROF_ACC_STATUS_BUS_PMU_START_NOT_CALLED; } else { /* Set mode to halt */ esrValue = GET_PMU_ESR; SET_PMU_MODE(esrValue, IX_PERFPROF_ACC_BUS_PMU_MODE_HALT); SET_PMU_ESR(esrValue); /* Verify if the ESR has been set to halt mode */ if (((GET_PMU_ESR) & ESR_MODE_MASK) != IX_PERFPROF_ACC_BUS_PMU_MODE_HALT) { ixPerfProfAccUnlock(); return IX_PERFPROF_ACC_STATUS_FAIL; } else { /* Unbind the interrupt */ ixOsalIrqUnbind(IX_OSAL_IXP400_AHB_PMU_IRQ_LVL); startFlag = FALSE ; ixPerfProfAccUnlock(); #ifdef __vxworks IX_OSAL_MEM_UNMAP(esrVirtualAddress); IX_OSAL_MEM_UNMAP(srVirtualAddress); #endif return IX_PERFPROF_ACC_STATUS_SUCCESS; } } /* End of if-else */} /* End of function ixPerfProfAccBusPmuStop*//* Function that returns the values required by the calling function */PUBLIC voidixPerfProfAccBusPmuResultsGet (IxPerfProfAccBusPmuResults *BusPmuResults){ int pecCounter; IxFeatureCtrlDeviceId deviceType=IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X; deviceType = ixFeatureCtrlDeviceRead (); if(IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X == deviceType) { IX_PERFPROF_ACC_LOG( IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixPerfProfAcc - This PPU component is not supported\n", 0, 0, 0, 0, 0, 0); return; } /*error check the parameter*/ if (NULL == BusPmuResults) { /* report the error */ IX_PERFPROF_ACC_LOG( IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixPerfProfAccBusPmuResultsGet - BusPmuResults is invalid\n", 0, 0, 0, 0, 0, 0); return; } #ifdef __vxworks for (pecCounter = 0; IX_PERFPROF_ACC_BUS_PMU_MAX_PECS > pecCounter; pecCounter++) { pecVirtualAddress = (UINT32)IX_OSAL_MEM_MAP(PMU_CNT_ADDR(pecCounter+1), IX_OSAL_IXP400_PMU_MAP_SIZE); BusPmuResults->statsToGetLower27Bit[pecCounter] = PMU_CNT_GET(); BusPmuResults->statsToGetUpper32Bit[pecCounter] = upper32BitCounter[pecCounter]; IX_OSAL_MEM_UNMAP(pecVirtualAddress); } #elif defined(__linux) for (pecCounter = 0; IX_PERFPROF_ACC_BUS_PMU_MAX_PECS > pecCounter; pecCounter++) { BusPmuResults->statsToGetLower27Bit[pecCounter] = PMU_CNT_GET(pecCounter+1); BusPmuResults->statsToGetUpper32Bit[pecCounter] = upper32BitCounter[pecCounter]; } #endif /* __vxworks */} /* End of function ixPerfProfAccBusPmuResultsGet */PUBLIC voidixPerfProfAccBusPmuPMSRGet (UINT32 *pmsrValue){ IxFeatureCtrlDeviceId deviceType=IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X; deviceType = ixFeatureCtrlDeviceRead (); if(IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X == deviceType) { IX_PERFPROF_ACC_LOG( IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixPerfProfAcc - This PPU component is not supported\n", 0, 0, 0, 0, 0, 0); return; } /*error check the parameter*/ if (NULL == pmsrValue) { /* report the error */ IX_PERFPROF_ACC_LOG( IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixPerfProfAccBusPmuPMSRGet - pmsrValue is invalid\n", 0, 0, 0, 0, 0, 0); return; } /* Get virtual address that is mapped depending on LE or BE */ #ifdef __vxworks pmsrVirtualAddress = (UINT32)IX_OSAL_MEM_MAP(PMU_PMSR,IX_OSAL_IXP400_PMU_MAP_SIZE); #endif /* Assign PMSR value to pointer */ *pmsrValue = PMU_CNT_PMSR(); /* Release dynamic virtual address mapping */ #ifdef __vxworks IX_OSAL_MEM_UNMAP(pmsrVirtualAddress); #endif}/* Interrupt handler routine. */voidixPerfProfAccBusPmuPecOverflowHdlr (void *voidParam){ UINT32 statusRegisterValue; UINT32 maskingBit; int pecCounter; /* Read value of the status register */ statusRegisterValue = GET_SR(); SR_RESET(); maskingBit = STATUS_REGISTER_BIT1_MASK; for (pecCounter = 0; IX_PERFPROF_ACC_BUS_PMU_MAX_PECS > pecCounter; pecCounter++) { if (statusRegisterValue & maskingBit) { upper32BitCounter[pecCounter] += 1; } maskingBit *= 2; }}/* end of ixPerfProfAccBusPmuPecOverflowHdlr */
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