ixperfprofaccbuspmu.c

有关ARM开发板上的IXP400网络驱动程序的源码以。

/**
 * @file IxPerfProfAccBusPmu.c
 *
 * @brief  Source file for the Xscale Bus PMU
 *
 *
 * Design Notes:
 *
 * 
 * @par
 * IXP400 SW Release version 2.1
 * 
 * -- Copyright Notice --
 * 
 * @par
 * Copyright (c) 2001-2005, Intel Corporation.
 * All rights reserved.
 * 
 * @par
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 
 * 
 * @par
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * 
 * @par
 * -- End of Copyright Notice --
 */

#include "IxPerfProfAcc.h"
#include "IxFeatureCtrl.h"
#include "IxPerfProfAccBusPmu_p.h"
#include "IxPerfProfAcc_p.h"
#include "IxOsal.h"

#define IX_PERFPROF_ACC_BUS_PMU_MAX_EVENTS IX_PERFPROF_ACC_BUS_PMU_PEC7_CYCLE_COUNT_SELECT

static BOOL startFlag = FALSE;

static UINT32
ixPerfProfAccBusPmuEventMap[IX_PERFPROF_ACC_BUS_PMU_MAX_EVENTS + 1] = {
    0,                  /* ENUM starts at 1, there is no entry for location [0] */
    PEC1_NORTH_NPEA_GRANT,  /*IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEA_GRANT_SELECT*/
    PEC1_NORTH_NPEB_GRANT,  /*IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEB_GRANT_SELECT*/
    PEC1_NORTH_NPEC_GRANT,  /*IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEC_GRANT_SELECT*/
    PEC1_NORTH_BUS_IDLE,    /*IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_BUS_IDLE_SELECT*/
    PEC1_NORTH_NPEA_REQ,    /*IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEA_REQ_SELECT*/
    PEC1_NORTH_NPEB_REQ,    /*IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEB_REQ_SELECT*/
    PEC1_NORTH_NPEC_REQ,    /*IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEC_REQ_SELECT*/

    PEC1_SOUTH_GSKT_GRANT,  /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_GSKT_GRANT_SELECT*/
    PEC1_SOUTH_ABB_GRANT,   /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_ABB_GRANT_SELECT*/
    PEC1_SOUTH_PCI_GRANT,   /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_PCI_GRANT_SELECT*/
    PEC1_SOUTH_APB_GRANT,   /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_APB_GRANT_SELECT*/
    PEC1_SOUTH_GSKT_REQ,    /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_GSKT_REQ_SELECT*/
    PEC1_SOUTH_ABB_REQ,     /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_ABB_REQ_SELECT*/
    PEC1_SOUTH_PCI_REQ,     /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_PCI_REQ_SELECT*/
    PEC1_SOUTH_APB_REQ,     /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_APB_REQ_SELECT*/

    PEC1_SDR_0_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_0_HIT_SELECT*/
    PEC1_SDR_1_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_1_HIT_SELECT*/
    PEC1_SDR_2_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_2_HIT_SELECT*/
    PEC1_SDR_3_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_3_HIT_SELECT*/
    PEC1_SDR_4_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_4_MISS_SELECT*/
    PEC1_SDR_5_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_5_MISS_SELECT*/
    PEC1_SDR_6_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_6_MISS_SELECT*/
    PEC1_SDR_7_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_7_MISS_SELECT*/

    PEC2_NORTH_NPEA_XFER,   /*IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEA_XFER_SELECT*/
    PEC2_NORTH_NPEB_XFER,   /*IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEB_XFER_SELECT*/
    PEC2_NORTH_NPEC_XFER,   /*IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEC_XFER_SELECT*/
    PEC2_NORTH_BUS_WRITE,   /*IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_BUS_WRITE_SELECT*/
    PEC2_NORTH_NPEA_OWN,    /*IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEA_OWN_SELECT*/
    PEC2_NORTH_NPEB_OWN,    /*IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEB_OWN_SELECT*/
    PEC2_NORTH_NPEC_OWN,    /*IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEC_OWN_SELECT*/

    PEC2_SOUTH_GSKT_XFER,   /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_GSKT_XFER_SELECT*/
    PEC2_SOUTH_ABB_XFER,    /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_ABB_XFER_SELECT*/
    PEC2_SOUTH_PCI_XFER,    /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_PCI_XFER_SELECT*/
    PEC2_SOUTH_APB_XFER,    /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_APB_XFER_SELECT*/
    PEC2_SOUTH_GSKT_OWN,    /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_GSKT_OWN_SELECT*/
    PEC2_SOUTH_ABB_OWN,     /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_ABB_OWN_SELECT*/
    PEC2_SOUTH_PCI_OWN,     /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_PCI_OWN_SELECT*/
    PEC2_SOUTH_APB_OWN,     /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_APB_OWN_SELECT*/

    PEC2_SDR_1_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_1_HIT_SELECT*/
    PEC2_SDR_2_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_2_HIT_SELECT*/
    PEC2_SDR_3_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_3_HIT_SELECT*/
    PEC2_SDR_4_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_4_HIT_SELECT*/
    PEC2_SDR_5_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_5_MISS_SELECT*/
    PEC2_SDR_6_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_6_MISS_SELECT*/
    PEC2_SDR_7_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_7_MISS_SELECT*/
    PEC2_SDR_0_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_0_MISS_SELECT*/

    PEC3_NORTH_NPEA_RETRY,  /*IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEA_RETRY_SELECT*/
    PEC3_NORTH_NPEB_RETRY,  /*IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEB_RETRY_SELECT*/
    PEC3_NORTH_NPEC_RETRY,  /*IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEC_RETRY_SELECT*/
    PEC3_NORTH_BUS_READ,    /*IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_BUS_READ_SELECT*/
    PEC3_NORTH_NPEA_WRITE,  /*IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEA_WRITE_SELECT*/
    PEC3_NORTH_NPEB_WRITE,  /*IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEB_WRITE_SELECT*/
    PEC3_NORTH_NPEC_WRITE,  /*IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEC_WRITE_SELECT*/

    PEC3_SOUTH_GSKT_RETRY,  /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_GSKT_RETRY_SELECT*/
    PEC3_SOUTH_ABB_RETRY,   /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_ABB_RETRY_SELECT*/
    PEC3_SOUTH_PCI_RETRY,   /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_PCI_RETRY_SELECT*/
    PEC3_SOUTH_APB_RETRY,   /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_APB_RETRY_SELECT*/
    PEC3_SOUTH_GSKT_WRITE,  /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_GSKT_WRITE_SELECT*/
    PEC3_SOUTH_ABB_WRITE,   /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_ABB_WRITE_SELECT*/
    PEC3_SOUTH_PCI_WRITE,   /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_PCI_WRITE_SELECT*/
    PEC3_SOUTH_APB_WRITE,   /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_APB_WRITE_SELECT*/

    PEC3_SDR_2_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_2_HIT_SELECT*/
    PEC3_SDR_3_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_3_HIT_SELECT*/
    PEC3_SDR_4_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_4_HIT_SELECT*/
    PEC3_SDR_5_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_5_HIT_SELECT*/
    PEC3_SDR_6_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_6_MISS_SELECT*/
    PEC3_SDR_7_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_7_MISS_SELECT*/
    PEC3_SDR_0_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_0_MISS_SELECT*/
    PEC3_SDR_1_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_1_MISS_SELECT*/

    PEC4_SOUTH_PCI_SPLIT,   /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_PCI_SPLIT_SELECT*/
    PEC4_SOUTH_EXP_SPLIT,   /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_EXP_SPLIT_SELECT*/
    PEC4_SOUTH_APB_GRANT,   /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_GRANT_SELECT*/
    PEC4_SOUTH_APB_XFER,    /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_XFER_SELECT*/
    PEC4_SOUTH_GSKT_READ,   /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_GSKT_READ_SELECT*/
    PEC4_SOUTH_ABB_READ,    /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_ABB_READ_SELECT*/
    PEC4_SOUTH_PCI_READ,    /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_PCI_READ_SELECT*/
    PEC4_SOUTH_APB_READ,    /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_READ_SELECT*/

    PEC4_NORTH_ABB_SPLIT,   /*IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_ABB_SPLIT_SELECT*/
    PEC4_NORTH_NPEA_REQ,    /*IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEA_REQ_SELECT*/
    PEC4_NORTH_NPEA_READ,   /*IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEA_READ_SELECT*/
    PEC4_NORTH_NPEB_READ,   /*IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEB_READ_SELECT*/
    PEC4_NORTH_NPEC_READ,   /*IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEC_READ_SELECT*/

    PEC4_SDR_3_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_3_HIT_SELECT*/
    PEC4_SDR_4_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_4_HIT_SELECT*/
    PEC4_SDR_5_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_5_HIT_SELECT*/
    PEC4_SDR_6_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_6_HIT_SELECT*/
    PEC4_SDR_7_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_7_MISS_SELECT*/
    PEC4_SDR_0_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_0_MISS_SELECT*/
    PEC4_SDR_1_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_1_MISS_SELECT*/
    PEC4_SDR_2_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_2_MISS_SELECT*/

    PEC5_SOUTH_ABB_GRANT,   /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_GRANT_SELECT*/
    PEC5_SOUTH_ABB_XFER,    /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_XFER_SELECT*/
    PEC5_SOUTH_ABB_RETRY,   /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_RETRY_SELECT*/
    PEC5_SOUTH_EXP_SPLIT,   /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_EXP_SPLIT_SELECT*/
    PEC5_SOUTH_ABB_REQ,     /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_REQ_SELECT*/
    PEC5_SOUTH_ABB_OWN,     /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_OWN_SELECT*/
    PEC5_SOUTH_BUS_IDLE,    /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_BUS_IDLE_SELECT*/

    PEC5_NORTH_NPEB_GRANT,  /*IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_GRANT_SELECT*/
    PEC5_NORTH_NPEB_XFER,   /*IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_XFER_SELECT*/
    PEC5_NORTH_NPEB_RETRY,  /*IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_RETRY_SELECT*/
    PEC5_NORTH_NPEB_REQ,    /*IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_REQ_SELECT*/
    PEC5_NORTH_NPEB_OWN,    /*IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_OWN_SELECT*/
    PEC5_NORTH_NPEB_WRITE,  /*IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_WRITE_SELECT*/
    PEC5_NORTH_NPEB_READ,   /*IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_READ_SELECT*/

    PEC5_SDR_4_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_4_HIT_SELECT*/
    PEC5_SDR_5_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_5_HIT_SELECT*/
    PEC5_SDR_6_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_6_HIT_SELECT*/
    PEC5_SDR_7_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_7_HIT_SELECT*/
    PEC5_SDR_0_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_0_MISS_SELECT*/
    PEC5_SDR_1_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_1_MISS_SELECT*/
    PEC5_SDR_2_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_2_MISS_SELECT*/
    PEC5_SDR_3_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_3_MISS_SELECT*/

    PEC6_SOUTH_PCI_GRANT,   /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_GRANT_SELECT*/
    PEC6_SOUTH_PCI_XFER,    /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_XFER_SELECT*/
    PEC6_SOUTH_PCI_RETRY,   /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_RETRY_SELECT*/
    PEC6_SOUTH_PCI_SPLIT,   /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_SPLIT_SELECT*/
    PEC6_SOUTH_PCI_REQ,     /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_REQ_SELECT*/
    PEC6_SOUTH_PCI_OWN,     /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_OWN_SELECT*/
    PEC6_SOUTH_BUS_WRITE,   /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_BUS_WRITE_SELECT*/

    PEC6_NORTH_NPEC_GRANT,  /*IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_GRANT_SELECT*/
    PEC6_NORTH_NPEC_XFER,   /*IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_XFER_SELECT*/
    PEC6_NORTH_NPEC_RETRY,  /*IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_RETRY_SELECT*/
    PEC6_NORTH_NPEC_REQ,    /*IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_REQ_SELECT*/
    PEC6_NORTH_NPEC_OWN,    /*IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_OWN_SELECT*/
    PEC6_NORTH_NPEB_WRITE,  /*IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEB_WRITE_SELECT*/
    PEC6_NORTH_NPEC_READ,   /*IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_READ_SELECT*/

    PEC6_SDR_5_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_5_HIT_SELECT*/
    PEC6_SDR_6_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_6_HIT_SELECT*/
    PEC6_SDR_7_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_7_HIT_SELECT*/
    PEC6_SDR_0_HIT,         /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_0_HIT_SELECT*/
    PEC6_SDR_1_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_1_MISS_SELECT*/
    PEC6_SDR_2_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_2_MISS_SELECT*/
    PEC6_SDR_3_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_3_MISS_SELECT*/
    PEC6_SDR_4_MISS,        /*IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_4_MISS_SELECT*/

    PEC7_SOUTH_APB_RETRY,   /*IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_RETRY_SELECT*/
    PEC7_SOUTH_APB_REQ,     /*IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_REQ_SELECT*/
    PEC7_SOUTH_APB_OWN,     /*IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_OWN_SELECT*/
    PEC7_SOUTH_BUS_READ,    /*IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_BUS_READ_SELECT*/
    PEC7_SOUTH_CYCLE_COUNT  /*IX_PERFPROF_ACC_BUS_PMU_PEC7_CYCLE_COUNT_SELECT*/
};


/* This function places all the input parameter into a structure,
 * and calls the setup function to set all the registers.
 **/
PUBLIC IxPerfProfAccStatus
ixPerfProfAccBusPmuStart (
    IxPerfProfAccBusPmuMode mode,
    IxPerfProfAccBusPmuEventCounters1 pecEvent1,
    IxPerfProfAccBusPmuEventCounters2 pecEvent2,
    IxPerfProfAccBusPmuEventCounters3 pecEvent3,
    IxPerfProfAccBusPmuEventCounters4 pecEvent4,
    IxPerfProfAccBusPmuEventCounters5 pecEvent5,
    IxPerfProfAccBusPmuEventCounters6 pecEvent6,
    IxPerfProfAccBusPmuEventCounters7 pecEvent7)
{

    UINT32 PecCounter; /* Variable to increment in the for loop */

    IxPerfProfAccBusPmuModeEvents eventsPerCounter;
    IxPerfProfAccStatus status;
    IxFeatureCtrlDeviceId deviceType=IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X;

    deviceType = ixFeatureCtrlDeviceRead();
    if(IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X == deviceType)
    {
        IX_PERFPROF_ACC_LOG(
            IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR,
            "ixPerfProfAcc - This PPU component is not supported\n",
            0, 0, 0, 0, 0, 0);
	return IX_PERFPROF_ACC_STATUS_COMPONENT_NOT_SUPPORTED;
    }
       
    #ifdef __vxworks
    /* Initialize all virtual addresses for vxWorks */
    esrVirtualAddress =  (UINT32)IX_OSAL_MEM_MAP(PMU_ESR,IX_OSAL_IXP400_PMU_MAP_SIZE);