ixparityenaccpbcpe.c

有关ARM开发板上的IXP400网络驱动程序的源码以。

                    ixParityENAccIcInterruptDisable(
                        IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT);
    }
    else
    {
        return IX_FAIL;
    } /* end of if */
} /* end of ixParityENAccPbcPEDetectionConfigure() function */


IX_STATUS
ixParityENAccPbcPEParityErrorContextFetch(
    IxParityENAccPbcPEParityErrorContext *ixPbcPECMsg)
{
    BOOL isrPPE   = FALSE;
    BOOL srcrDPE  = FALSE;
    BOOL srcrMDPE = FALSE;

    if ((IxParityENAccPbcPEParityErrorContext *)NULL == ixPbcPECMsg)
    {
        return IX_FAIL;
    } /* end of if */

    /* Fetch PBC Parity Error Status into local data structures*/
    ixParityENAccPbcPEParityErrorStatusGet();

    /*
     * PCI Controller Initiator/Target Interface and Parity Errors detection
     * during Read / Write Transactions show in the following decision table 
     *
     *             +--------------------+--------------------+
     *             |    PCI Initiator   |     PCI Target     |
     *             +----------+---------+----------+---------+
     *             |    Read  |  Write  |   Read   |  Write  |
     *             +----------+---------+----------+---------+
     *   isr.PPE   |     1    |    1    |     -    |    1    |
     *             +----------+---------+----------+---------+
     *  srcr.DPE   |     1    |    0    |     -    |    1    |
     *             +----------+---------+----------+---------+
     *  srcr.MDPE  |     1    |    1    |     -    |    0    |
     *             +----------+---------+----------+---------+
     *
     * While:
     *        -   Error handling is left to initiator of transaction
     *        1   Bit in the register (row heading-reg.BIT) is SET
     *        0   Bit in the register is CLEAR
     *        x   Don't Care
     */

    isrPPE   = IXP400_PARITYENACC_VAL_BIT_CHECK(
                   ixParityENAccPbcPEConfig.pbcParityErrorStatus.pciIsrValue,
                   (UINT32) IXP400_PARITYENACC_PBC_ISR_PPE);

    srcrDPE  = IXP400_PARITYENACC_VAL_BIT_CHECK(
                   ixParityENAccPbcPEConfig.pbcParityErrorStatus.pciSrcrValue,
                   (UINT32) IXP400_PARITYENACC_PBC_PCICFG_SRCR_DPE);

    srcrMDPE = IXP400_PARITYENACC_VAL_BIT_CHECK(
                   ixParityENAccPbcPEConfig.pbcParityErrorStatus.pciSrcrValue,
                   (UINT32) IXP400_PARITYENACC_PBC_PCICFG_SRCR_MDPE);

    /* Is Parity Error Detected ? */
    if (TRUE == isrPPE)
    {
        /* Is due to PCI Initiator Transaction ? */
        if (TRUE == srcrMDPE)
        {
            /* Is due to PCI Initiator Read Transaction ? */
            if (TRUE == srcrDPE)
            {
                ixPbcPECMsg->pbcParitySource = IXP400_PARITYENACC_PE_PBC_INITIATOR;
                ixPbcPECMsg->pbcAccessType   = IXP400_PARITYENACC_PE_READ;
                return IX_SUCCESS;
            } /* else of if */
            /* Is due to PCI Initiator Write Transaction ? */
            else
            {
                ixPbcPECMsg->pbcParitySource = IXP400_PARITYENACC_PE_PBC_INITIATOR;
                ixPbcPECMsg->pbcAccessType   = IXP400_PARITYENACC_PE_WRITE;
                return IX_SUCCESS;
            } /* end of if */            
        } /* end of if */

        /* Is due to PCI Target Write Transaction ? */
        if (TRUE == srcrDPE)
        {
            ixPbcPECMsg->pbcParitySource = IXP400_PARITYENACC_PE_PBC_TARGET;
            ixPbcPECMsg->pbcAccessType   = IXP400_PARITYENACC_PE_WRITE;
            return IX_SUCCESS;
        } /* end of if */

        /* Is due to PCI Target Read Transaction? Possibly */
        ixPbcPECMsg->pbcParitySource = IXP400_PARITYENACC_PE_PBC_TARGET;
        ixPbcPECMsg->pbcAccessType   = IXP400_PARITYENACC_PE_READ;
        return IX_SUCCESS;
    } /* end of if */

#ifndef NDEBUG
    IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR,
        "ixParityENAccPbcPEParityErrorContextFetch(): "
        "Can't fetch parity context of PBC !!!\n", 0,0,0,0,0,0);
#endif /* end of #ifndef NDEBUG */

    return IX_FAIL;
} /* end of function */

IX_STATUS
ixParityENAccPbcPEParityInterruptClear (
    IxParityENAccPbcPEParityErrorContext ixPbcPECMsg)
{
    IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
        "\nixParityENAccPbcPEParityInterruptClear():"
        "\n\tpbcParitySource:%x\tpbcAccessType:%x\n", 
        ixPbcPECMsg.pbcParitySource,ixPbcPECMsg.pbcAccessType,0,0,0,0);
        	
    IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_DEBUG2, IX_OSAL_LOG_DEV_STDOUT,
        "ixParityENAccPbcPEParityInterruptClear(): "
        "\nIXP400_PARITYENACC_PE_PBC_INITIATOR:%x"
        "\tIXP400_PARITYENACC_PE_READ:%x\n", 
        (IXP400_PARITYENACC_PE_PBC_INITIATOR),(IXP400_PARITYENACC_PE_READ),0,0,0,0);
        	
    /* Clear off Parity Error Status due to PCI Initiator Read? */
    if (IXP400_PARITYENACC_PE_PBC_INITIATOR == ixPbcPECMsg.pbcParitySource)
    {
        /* Write '1' to clear off the srcr.MDPE and srcr.DPE */
        IXP400_PARITYENACC_VAL_BIT_SET(
            ixParityENAccPbcPEConfig.pbcParityErrorStatus.pciSrcrValue,
            (IXP400_PARITYENACC_PBC_PCICFG_SRCR_MDPE | 
            IXP400_PARITYENACC_PBC_PCICFG_SRCR_DPE) );
    } /* end of if */

    /* Clear off Parity Error Status due to PCI Target Write? */
    if (IXP400_PARITYENACC_PE_PBC_TARGET == ixPbcPECMsg.pbcParitySource)
    {
        /* Write '1' to clear off the srcr.DPE */
        IXP400_PARITYENACC_VAL_BIT_SET(
            ixParityENAccPbcPEConfig.pbcParityErrorStatus.pciSrcrValue,
            IXP400_PARITYENACC_PBC_PCICFG_SRCR_DPE);
    } /* end of if */

    /* Clear parity error interrupt status */
    ixParityENAccPbcPEParityErrorStatusClear();

    return IX_SUCCESS;
} /* end of ixParityENAccPbcPEParityInterruptClear() function */


/*
 * Local functions definitions
 */

void 
ixParityENAccPbcPEIsr(void)
{
    /*
     * No need to read parity error status from the Parity Status Register
     *
     * Invoke the internal PBC callback routine to notify the parity error 
     * detected on the PCI Initiator or PCI Target Interface
     * 
     * NOTE: The PBC parity error context information will be obtained only 
     * when the public API client application requests for such information.
     */
    (*ixParityENAccPbcPEConfig.pbcPECallback)(
        ixParityENAccPbcPEConfig.pbcIsrInfo.pbcInterruptId,
        ixParityENAccPbcPEConfig.pbcIsrInfo.pbcIsr);
} /* end of ixParityENAccPbcPEIsr() function */

/* Get parity error status into internal datastructures */
void
ixParityENAccPbcPEParityErrorStatusGet (void)
{
    register IxParityENAccPbcPERegisters *pbcPERegisters =
        &ixParityENAccPbcPEConfig.pbcPERegisters;
    register IxParityENAccPbcPEParityErrorStatus *pbcPEErrSts =
        &ixParityENAccPbcPEConfig.pbcParityErrorStatus;

    /* Read PCI Controller Interrupt Enable Register contents */
    IXP400_PARITYENACC_REG_READ(pbcPERegisters->pciInten, &pbcPEErrSts->pciIntenValue);

    /* Read PCI Controller Interrupt Status Register contents */
    IXP400_PARITYENACC_REG_READ(pbcPERegisters->pciIsr, &pbcPEErrSts->pciIsrValue);

    /* Read PCI Controller Control and Status Register contents */
    IXP400_PARITYENACC_REG_READ(pbcPERegisters->pciCsr, &pbcPEErrSts->pciCsrValue);

    /* Read the PCI Controller PCI Config SRCR register */
    IXP400_PARITYENACC_REG_WRITE(pbcPERegisters->pciCrpAdCbe,
        IXP400_PARITYENACC_PBC_PCICSR_SRCR_READ);
    IXP400_PARITYENACC_REG_READ(pbcPERegisters->pciCrpRdata, &pbcPEErrSts->pciSrcrValue);
} /* end of ixParityENAccPbcPEParityErrorStatusGet() function */

/* Set parity error interrupt status to clear */
void 
ixParityENAccPbcPEParityErrorStatusClear (void)
{
    /* Update the PCI Controller PCI Config SRCR register */
   IXP400_PARITYENACC_REG_WRITE(ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe,
        IXP400_PARITYENACC_PBC_PCICSR_SRCR_WRITE);    
    IXP400_PARITYENACC_REG_WRITE(ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpWdata,
        ixParityENAccPbcPEConfig.pbcParityErrorStatus.pciSrcrValue);
 
    /* Clear off Parity Error Interrupt Status by writing '1' onto PPE bit */
    IXP400_PARITYENACC_REG_BIT_SET(ixParityENAccPbcPEConfig.pbcPERegisters.pciIsr,
        IXP400_PARITYENACC_PBC_ISR_PPE);
} /* end of ixParityENAccPbcPEParityErrorStatusClear() function */

#endif /* __ixp46X */