ixparityenaccpbcpe.c

有关ARM开发板上的IXP400网络驱动程序的源码以。

/**
 * @file IxParityENAccPbcPE.c
 *
 * @author Intel Corporation
 * @date 26 July 2004
 *
 * @brief Source file for PBC Parity Detection Enabler sub-component 
 * of the IXP400 Parity Error Notifier access component.
 *
 * @par
 * IXP400 SW Release version 2.1
 * 
 * -- Copyright Notice --
 * 
 * @par
 * Copyright (c) 2001-2005, Intel Corporation.
 * All rights reserved.
 * 
 * @par
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 
 * 
 * @par
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * 
 * @par
 * -- End of Copyright Notice --
 */

#ifdef __ixp46X

/* 
 * System defined include files
 */
#include "IxOsal.h"

/*
 * User defined include files
 */
#include "IxParityENAccIcE.h"
#include "IxParityENAccPbcPE.h"
#include "IxParityENAccPbcPE_p.h"


/*
 * PBC sub-module level functions definitions
 */

IX_STATUS
ixParityENAccPbcPEInit(IxParityENAccInternalCallback ixPbcPECallback)
{
    UINT32 pbcVirtualBaseAddr = 0;
    register IxParityENAccPbcPERegisters *pbcPERegisters =
        &ixParityENAccPbcPEConfig.pbcPERegisters;
    
    /* Verify parameters */
    if ((IxParityENAccInternalCallback)NULL == ixPbcPECallback)
    {
        return IX_FAIL;
    } /* end of if */

    /* Memory mapping of the PBC registers */
    if ((UINT32)NULL == (pbcVirtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP (
                                              IXP400_PARITYENACC_PBC_PCICSR_BASEADDR,
                                              IXP400_PARITYENACC_PBC_PCICSR_MEMMAP_SIZE)))
    {
        return IX_FAIL;
    } /* end of if */

    /* Virtual Addresses assignment for PBC Control and Status Registers */
    pbcPERegisters->pciCrpAdCbe = 
        pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CRP_AD_CBE_OFFSET;
    pbcPERegisters->pciCrpWdata = 
        pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CRP_WDATA_OFFSET;
    pbcPERegisters->pciCrpRdata = 
        pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CRP_RDATA_OFFSET;
    pbcPERegisters->pciCsr = 
        pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CSR_OFFSET;
    pbcPERegisters->pciIsr = 
        pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_ISR_OFFSET;
    pbcPERegisters->pciInten = 
        pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_INTEN_OFFSET;

    /* Register main module internal callback routine */
    ixParityENAccPbcPEConfig.pbcPECallback = ixPbcPECallback;

    /* Interrupt Service Routine Info for debug purpose */
    ixParityENAccPbcPEConfig.pbcIsrInfo.pbcInterruptId = 
        IRQ_IXP400_INTC_PARITYENACC_PBC;
    ixParityENAccPbcPEConfig.pbcIsrInfo.pbcIsr = ixParityENAccPbcPEIsr;

    /* Disable parity error detection */

    /* Write '1' to clear-off the PPE bit */
    IXP400_PARITYENACC_REG_BIT_SET(
        pbcPERegisters->pciIsr, IXP400_PARITYENACC_PBC_ISR_PPE);

    IXP400_PARITYENACC_REG_BIT_CLEAR(
        pbcPERegisters->pciInten, IXP400_PARITYENACC_PBC_INTEN_PPE);

    /* Install PBC Interrupt Service Routine */
    {
        INT32 lockKey = ixOsalIrqLock();
        if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_PBC,
                                        (IxOsalVoidFnVoidPtr) ixParityENAccPbcPEIsr,
                                        (void *) NULL)) ||
            (IX_FAIL == ixParityENAccIcInterruptDisable(
                        IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT)))
        {
            ixOsalIrqUnlock(lockKey);
            IX_OSAL_MEM_UNMAP(pbcVirtualBaseAddr);
            return IX_FAIL;
        } /* end of if */
        ixOsalIrqUnlock(lockKey);
    }

    return IX_SUCCESS;
} /* end of ixParityENAccPbcPEInit() function */

IX_STATUS
ixParityENAccPbcPEDetectionConfigure(IxParityENAccPbcPEConfigOption ixPbcPDCfg)
{
    UINT32 pbcPDCfgStatus = 0;
    UINT32 pbcTmpPDCfgStatus = 0;
    int    loopIdx = 0;

    /* Read the PCI Controller PCI Config SRCR register */
    IXP400_PARITYENACC_REG_WRITE(
        ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe,
        IXP400_PARITYENACC_PBC_PCICSR_SRCR_READ);
    IXP400_PARITYENACC_REG_READ(
        ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpRdata,
        &pbcPDCfgStatus);

    /* 
     * Set/Clear the PER bit of SRCR register & 
     * Enable/Disable Parity Error Notification
     */
    if (IXP400_PARITYENACC_PE_ENABLE == ixPbcPDCfg)
    {
        /* Set the PER bit of SRCR register */
        IXP400_PARITYENACC_VAL_BIT_SET(pbcPDCfgStatus, 
            IXP400_PARITYENACC_PBC_PCICFG_SRCR_PER);

        /* Enable the PCI Parity Error Interrupt Notification */
        IXP400_PARITYENACC_REG_BIT_SET(
            ixParityENAccPbcPEConfig.pbcPERegisters.pciInten,
            IXP400_PARITYENACC_PBC_INTEN_PPE);
    } 
    /* else of if */
    else
    {
        /* Clear the PER bit of SRCR register */
        IXP400_PARITYENACC_VAL_BIT_CLEAR(pbcPDCfgStatus,
            IXP400_PARITYENACC_PBC_PCICFG_SRCR_PER);

        /* Disable the PCI Parity Error Interrupt Notification */
        IXP400_PARITYENACC_REG_BIT_CLEAR(
            ixParityENAccPbcPEConfig.pbcPERegisters.pciInten,
            IXP400_PARITYENACC_PBC_INTEN_PPE);
    } /* end of if */

    /* Write back the PCI Controller PCI Config SRCR register */
    IXP400_PARITYENACC_REG_WRITE(
        ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe,
        IXP400_PARITYENACC_PBC_PCICSR_SRCR_WRITE);
    IXP400_PARITYENACC_REG_WRITE(
        ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpWdata,
        pbcPDCfgStatus);

    loopIdx = 10;
    while (loopIdx--)
    {
        /* Verify that the configuration is successful or not */
        IXP400_PARITYENACC_REG_WRITE(
            ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe,
            IXP400_PARITYENACC_PBC_PCICSR_SRCR_READ);
        IXP400_PARITYENACC_REG_READ(
            ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpRdata,
            &pbcTmpPDCfgStatus);
    }

    if (TRUE == IXP400_PARITYENACC_VAL_BIT_CHECK(pbcPDCfgStatus, pbcTmpPDCfgStatus))
    {
        /* Enable/Disable the corresponding interrupt at Interrupt Controller */
        return (IXP400_PARITYENACC_PE_ENABLE == ixPbcPDCfg) ?
                    ixParityENAccIcInterruptEnable(
                        IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT) :