ixparityenaccmain.c

有关ARM开发板上的IXP400网络驱动程序的源码以。

/**
 * @file IxParityENAccMain.c
 *
 * @author Intel Corporation
 * @date 26 July 2004
 *
 * @brief  Source file for the Main sub-component of the IXP400 Parity 
 * Error Notifier access component.
 *
 * @par
 * IXP400 SW Release version 2.1
 * 
 * -- Copyright Notice --
 * 
 * @par
 * Copyright (c) 2001-2005, Intel Corporation.
 * All rights reserved.
 * 
 * @par
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 
 * 
 * @par
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * 
 * @par
 * -- End of Copyright Notice --
 */

#ifdef __ixp46X

/*
 * System include files
 */
#include "IxOsal.h"

/*
 * User defined include files
 */
#include "IxParityENAccMain.h"
#include "IxParityENAccNpePE.h"
#include "IxParityENAccPbcPE.h"
#include "IxParityENAccScpPE.h"
#include "IxParityENAccAqmPE.h"
#include "IxParityENAccMcuPE.h"
#include "IxParityENAccEbcPE.h"
#include "IxParityENAccIcE.h"
#include "IxParityENAccPmuE.h"
#include "IxFeatureCtrl.h"


/*
 * Variable declarations global to the Main sub-module
 */

/* IxParityENAcc module initialisation status */
static IxParityENAccInitStatus ixParityENAccInitStatus = FALSE;

/* Client callback routine */
static IxParityENAccCallback   ixParityENAccClientCb = NULL;

/* Fused-Out Modules */
static IxParityENAccFusedModules ixParityENAccFusedModules = 0;

/* Local instance of the configuration status of the hardware blocks */
static IxParityENAccParityConfigStatus ixParityENAccParityConfigStatus =
{
    /* NPE-A Configuration */
    { IX_PARITYENACC_DISABLE, IX_PARITYENACC_EVEN_PARITY }, 
    /* NPE-B Configuration */
    { IX_PARITYENACC_DISABLE, IX_PARITYENACC_EVEN_PARITY },
    /* NPE-C Configuration */
    { IX_PARITYENACC_DISABLE, IX_PARITYENACC_EVEN_PARITY },
    /* MCU ECC Configuration */
    { IX_PARITYENACC_DISABLE, IX_PARITYENACC_DISABLE, IX_PARITYENACC_DISABLE },
    /* SWCP Configuration */
    IX_PARITYENACC_DISABLE,
    /* AQM Configuration */
    IX_PARITYENACC_DISABLE,
    /* PBC Configuration */
    { IX_PARITYENACC_DISABLE, IX_PARITYENACC_DISABLE },
    /* EBC Configuration */
    {
        IX_PARITYENACC_DISABLE, IX_PARITYENACC_DISABLE,
        IX_PARITYENACC_DISABLE, IX_PARITYENACC_DISABLE,
        IX_PARITYENACC_DISABLE, IX_PARITYENACC_DISABLE,
        IX_PARITYENACC_DISABLE, IX_PARITYENACC_DISABLE,
        IX_PARITYENACC_DISABLE, IX_PARITYENACC_EVEN_PARITY
    }
};

static IxParityENAccPEParityErrorStats ixParityENAccPEParityErrorStats =
{
    { 0,0,0 },  /* NPE Stats */
    { 0,0,0 },  /* MCU Stats */
    { 0,0 },    /* PBC Stats */
    { 0,0 },    /* EBC Stats */
    0,          /* SWCP Stats */
    0           /* AQM Stats */
};

/*
 * Local functions declarations
 */
IX_STATUS
ixParityENAccConfigInit (void);

IX_STATUS
ixParityENAccModulesInit (void);

void 
ixParityENAccInvokeClientCallback (UINT32 irqNum);

/*
 * Local functions definitions
 */

/* 
 * Includes the fix to handle the NPE configuration hang issue 
 * with ethAcc END driver enabled in the bootrom and/or vxWorks.st 
 * which generates NPE related  parity errors prior to the NPE
 * parity detection configuration.
 */
/* Function to check and invoke the Client Callback Routine */
void ixParityENAccInvokeClientCallback (UINT32 irqNum)
{
    if ((IxParityENAccCallback)NULL != ixParityENAccClientCb)
    {
        if (TRUE != ixParityENAccInitStatus)
        {
            IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_ERROR,
                IX_OSAL_LOG_DEV_STDERR,
                "Initialisation is not yet complete (Status - %d)\n"
                "Interrupt #0x%x is being disabled", 
                ixParityENAccInitStatus,irqNum,0,0,0,0);
            ixOsalIrqDisable(irqNum);
        } 
        else
        {
            (*ixParityENAccClientCb)();
        } /* end of if */
    }
    else
    {
        IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_ERROR,
            IX_OSAL_LOG_DEV_STDERR,
            "NULL Client Callback!!!\n"
            "Interrupt #0x%x is being disabled", irqNum,0,0,0,0,0);
        ixOsalIrqDisable(irqNum);
    } /* end of if */
} /* end of ixParityENAccInvokeClientCallback () function */

IX_STATUS
ixParityENAccConfigInit (void)
{
    /* Check for IXP46X device */
    if (IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X != ixFeatureCtrlDeviceRead())
    {
        IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, 
            "ixParityENAccConfigInit(): "
            "Parity Error Notifier not supported on this device\n", 0,0,0,0,0,0);
        return IX_FAIL;
    } /* end of if */

    /* Find the fused-out module status
     *
     * NOTE: Feature Control uses #define IX_FEATURECTRL_ECC_TIMESYNC 
     * for both the ECC feature of SDRAM Controller and TimeSync.
     */
    if (IX_FEATURE_CTRL_COMPONENT_DISABLED == 
        ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ECC_TIMESYNC))
    {
        IXP400_PARITYENACC_VAL_BIT_SET(ixParityENAccFusedModules,
            IXP400_PARITYENACC_FUSED_MODULE_MCU_ECC);
    } /* end of if */

    if (IX_FEATURE_CTRL_COMPONENT_DISABLED == 
        ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA))
    {
        IXP400_PARITYENACC_VAL_BIT_SET(ixParityENAccFusedModules,
            IXP400_PARITYENACC_FUSED_MODULE_NPEA);
    } /* end of if */

    if (IX_FEATURE_CTRL_COMPONENT_DISABLED == 
        ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB))
    {
        IXP400_PARITYENACC_VAL_BIT_SET(ixParityENAccFusedModules,
            IXP400_PARITYENACC_FUSED_MODULE_NPEB);
    } /* end of if */

    if (IX_FEATURE_CTRL_COMPONENT_DISABLED == 
        ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC))
    {
        IXP400_PARITYENACC_VAL_BIT_SET(ixParityENAccFusedModules,
            IXP400_PARITYENACC_FUSED_MODULE_NPEC);
    } /* end of if */

    return IX_SUCCESS;
} /* end of ixParityENAccConfigInit() function */

IX_STATUS
ixParityENAccModulesInit (void)
{
    /*
     * This one is moved up in the Init chain due to the
     * interrupt disable function is being invoked by other
     * modules even before it was being initialised.
     */
    if (IX_SUCCESS != ixParityENAccIcEInit())
    {
        IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_DEBUG2, IX_OSAL_LOG_DEV_STDOUT,
            "ixParityENAccModulesInit(): INTC Configuration failed\n",0,0,0,0,0,0);
        return IX_FAIL;
    } /* end of if */

    if (IX_SUCCESS != ixParityENAccNpePEInit(ixNpePEInternalCallback))
    {
        IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_DEBUG2, IX_OSAL_LOG_DEV_STDOUT,
            "ixParityENAccModulesInit(): NPE Configuration failed\n",0,0,0,0,0,0);
        return IX_FAIL;
    } /* end of if */

    if (IX_SUCCESS != ixParityENAccSwcpPEInit(ixSwcpPEInternalCallback))
    {
        IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_DEBUG2, IX_OSAL_LOG_DEV_STDOUT,
            "ixParityENAccModulesInit(): SWCP Configuration failed\n",0,0,0,0,0,0);
        return IX_FAIL;
    } /* end of if */

    if (IX_SUCCESS != ixParityENAccAqmPEInit(ixAqmPEInternalCallback))
    {
        IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_DEBUG2, IX_OSAL_LOG_DEV_STDOUT,
            "ixParityENAccModulesInit(): AQM Configuration failed\n",0,0,0,0,0,0);
        return IX_FAIL;
    } /* end of if */

    if (IX_SUCCESS != ixParityENAccMcuPEInit(ixMcuPEInternalCallback))
    {
        IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_DEBUG2, IX_OSAL_LOG_DEV_STDOUT,
            "ixParityENAccModulesInit(): MCU Configuration failed\n",0,0,0,0,0,0);
        return IX_FAIL;
    } /* end of if */

    if (IX_SUCCESS != ixParityENAccPbcPEInit(ixPbcPEInternalCallback))
    {
        IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_DEBUG2, IX_OSAL_LOG_DEV_STDOUT,
            "ixParityENAccModulesInit(): PBC Configuration failed\n",0,0,0,0,0,0);
        return IX_FAIL;
    } /* end of if */

    if (IX_SUCCESS != ixParityENAccEbcPEInit(ixEbcPEInternalCallback))
    {
        IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_DEBUG2, IX_OSAL_LOG_DEV_STDOUT,
            "ixParityENAccModulesInit(): EBC Configuration failed\n",0,0,0,0,0,0);
        return IX_FAIL;
    } /* end of if */

    if (IX_SUCCESS != ixParityENAccPmuEInit())
    {
        IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_DEBUG2, IX_OSAL_LOG_DEV_STDOUT,
            "ixParityENAccModulesInit(): PMU Configuration failed\n",0,0,0,0,0,0);
        return IX_FAIL;
    } /* end of if */

    return IX_SUCCESS;
} /* end of ixParityENAccModulesInit() function */

void
ixMcuPEInternalCallback (UINT32 irqNum, IxParityENAccPEIsr isrAddr)
{
    IxParityENAccIcParityInterruptStatus ixIcEDummyStatus =
    { FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE };
    /*
     * Output the MCU interrupt information for debug purpose
     */
    IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
        "ixMcuPEInternalCallback(): MCU interrupt detected\n"
        "IRQ #:%x ISR Address:%p\n", irqNum, (UINT32)isrAddr, 0,0,0,0);

    /*
     * Add the Delay for Max Data/Prefetch Abort Exception to trigger
     * and complete before this interrupt service routine to avoid the
     * potential race conditions between the Exception Handler & ISR 
     *
     * The delay is introduced by a dummy read of one/more of the 
     * interrupt controller registers.
     */
    ixParityENAccIcInterruptStatusGet(&ixIcEDummyStatus);

    /* Inform the client application of the interrupt condition */
    ixParityENAccInvokeClientCallback(irqNum);
} /* end of ixMcuPEInternalCallback() function */

void
ixNpePEInternalCallback (UINT32 irqNum, IxParityENAccPEIsr isrAddr)
{
    /* Output the NPE interrupt information for debug purpose */
    IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
        "ixNpePEInternalCallback(): NPE interrupt detected\n"
        "IRQ #:%x ISR Address:%p\n", irqNum, (UINT32)isrAddr, 0,0,0,0);

    /* Signal the client application of the interrupt condition */
    ixParityENAccInvokeClientCallback(irqNum);