ixparityenaccnpepe.c

有关ARM开发板上的IXP400网络驱动程序的源码以。

    /* These WE bits are essential to update other flags */
    UINT32 npePDCtlFlags  = IXP400_PARITYENACC_NPE_CONTROL_IPEWE | 
                            IXP400_PARITYENACC_NPE_CONTROL_DPEWE |
                            IXP400_PARITYENACC_NPE_CONTROL_EEEWE |
                            IXP400_PARITYENACC_NPE_CONTROL_PPWE; 
    UINT32 npePDCfgStatus = 0;
    UINT32 npeTmpPDCfgStatus = 0;

    /* Validate parameters */
    if (ixNpeId >= IXP400_PARITYENACC_PE_NPE_MAX)
    {
        return IX_FAIL;
    } /* end of if */

    /* Get current parity detection configuration */
#ifdef __vxworks
    /* 
     * Fix to handle the NPE configuration hang issue with ethAcc END driver
     * enabled in the bootrom and/or vxWorks.st which generates NPE related
     * parity errors prior to the NPE parity detection configuration.
     */
    if (IX_FAIL == ixParityENAccIcInterruptDisable(
                       (IXP400_PARITYENACC_PE_NPE_A == ixNpeId) ? 
                           IXP400_PARITYENACC_INTC_NPEA_PARITY_INTERRUPT : 
                           (IXP400_PARITYENACC_PE_NPE_B == ixNpeId) ?
                               IXP400_PARITYENACC_INTC_NPEB_PARITY_INTERRUPT : 
                               IXP400_PARITYENACC_INTC_NPEC_PARITY_INTERRUPT))
    {
        return IX_FAIL;
    }
#endif

    /* Enable parity error detection */
    if (IXP400_PARITYENACC_PE_ENABLE == ixNpePDCfg.ideEnabled)
    {
        IXP400_PARITYENACC_VAL_BIT_SET(npePDCfgStatus, npePDCfgFlags);
    } 
    /* Disable parity error detection */
    else
    {
        IXP400_PARITYENACC_VAL_BIT_CLEAR(npePDCfgStatus,npePDCfgFlags);
    } /* end of if */

    /* Odd parity polarity */
    if (IX_PARITYENACC_ODD_PARITY == ixNpePDCfg.parityOddEven)
    {
        IXP400_PARITYENACC_VAL_BIT_SET(npePDCfgStatus,IXP400_PARITYENACC_NPE_CONTROL_PP);
    }
    else
    {
        IXP400_PARITYENACC_VAL_BIT_CLEAR(npePDCfgStatus,IXP400_PARITYENACC_NPE_CONTROL_PP);
    } /* end of if */

    /* Always include these bits for the parity error config changes to take place */
    IXP400_PARITYENACC_VAL_BIT_SET(npePDCfgStatus, npePDCtlFlags);

    /* Set the new configuration */
    IXP400_PARITYENACC_REG_WRITE (
        ixParityENAccNpePEConfig[ixNpeId].npePERegisters.npeControlRegister,
        npePDCfgStatus);

    IXP400_PARITYENACC_REG_READ(
        ixParityENAccNpePEConfig[ixNpeId].npePERegisters.npeControlRegister,
        &npeTmpPDCfgStatus);

    /*
     * These WE bits are read as zeros only so we need to clear them off from the value
     * we have just written so that compare gives correct result.
     */
    IXP400_PARITYENACC_VAL_BIT_CLEAR(npePDCfgStatus, npePDCtlFlags);

    /*
     * The extra bits other than the parity detection control bits/flags, if any, needs
     * to be cleared from the value just read so as to check for the correct parity 
     * detection control bits/flags for correct result.
     *
     * Example: Step 1. Written Value: 3c1c0000
     *          Step 2. ReadE 001c0000 (Expected)
     *          Step 3. ReadA 001d0000 (Actual)
     *          Step 4. ReadE != ReadA
     *          Fix: Step 1. Mask off with 3c00 0000 (as they are read zeros, refer to the
     *                       immediate above step in the code.)
     *               Step 2. Mask off bits other than parity detection control bits/flags
     *                       from the read value.
     *                       001c0000 (= 001d0000 & ~10000) here 10000 extracted using
     *                       (= 001d0000 & ~001c0000).
     *               Step 3. Now we can compare only the parity detection control bits/flags 
     *                       i.e., between written and read control bits.
     */
    {
        UINT32 npeTmpNonPDCfgStatus  = npeTmpPDCfgStatus;
        IXP400_PARITYENACC_VAL_BIT_CLEAR(npeTmpNonPDCfgStatus, npePDCfgStatus);
        IXP400_PARITYENACC_VAL_BIT_CLEAR(npeTmpPDCfgStatus, npeTmpNonPDCfgStatus);
    }

    if (npeTmpPDCfgStatus == npePDCfgStatus)
    {
        /* Enable/Disable the corresponding interrupt at Interrupt Controller */
        if (IXP400_PARITYENACC_PE_ENABLE == ixNpePDCfg.ideEnabled)
        {
            return ixParityENAccIcInterruptEnable( 
                       (IXP400_PARITYENACC_PE_NPE_A == ixNpeId) ? 
                            IXP400_PARITYENACC_INTC_NPEA_PARITY_INTERRUPT : 
                            (IXP400_PARITYENACC_PE_NPE_B == ixNpeId) ?
                                IXP400_PARITYENACC_INTC_NPEB_PARITY_INTERRUPT : 
                                IXP400_PARITYENACC_INTC_NPEC_PARITY_INTERRUPT);
        }
        else
        {
            return ixParityENAccIcInterruptDisable(
                       (IXP400_PARITYENACC_PE_NPE_A == ixNpeId) ? 
                            IXP400_PARITYENACC_INTC_NPEA_PARITY_INTERRUPT : 
                            (IXP400_PARITYENACC_PE_NPE_B == ixNpeId) ?
                                IXP400_PARITYENACC_INTC_NPEB_PARITY_INTERRUPT : 
                                IXP400_PARITYENACC_INTC_NPEC_PARITY_INTERRUPT);
        } /* end of if */
    }
    else
    {
        return IX_FAIL;
    } /* end of if */
} /* end of ixParityENAccNpePEDetectionConfigure() function */


IX_STATUS
ixParityENAccNpePEParityErrorContextFetch (
    IxParityENAccPENpeId ixNpeId,
    IxParityENAccNpePEParityErrorContext *ixNpePECMsg)
{
    /* Validate parameters */
    if ((ixNpeId >= IXP400_PARITYENACC_PE_NPE_MAX) ||
        ((IxParityENAccNpePEParityErrorContext *)NULL == ixNpePECMsg))
    {
        return IX_FAIL;
    } /* end of if */

    /* For NPEs it is always the read access to the IMEM/DMEM  */
    ixNpePECMsg->npeAccessType = IXP400_PARITYENACC_PE_READ;

    /* 
     * Identify parity errors detected from Status Register
     */

    /* Retrieve the raw parity error status */
    ixParityENAccNpePEParityErrorStatusGet();

    /*
     * NPE will be locked-up when any of the parity error is detected
     * Check the parity errors in the following order
     *
     * 1) Instruction Memory 2) Data Memory 3) External Error
     */
    if (IXP400_PARITYENACC_VAL_BIT_CHECK(
            ixParityENAccNpePEConfig[ixNpeId].npeParityErrorStatus.\
                npeStatusRegisterValue, (UINT32) IXP400_PARITYENACC_NPE_STATUS_IMEM_PARITY))
    {
        ixNpePECMsg->npeParitySource = IXP400_PARITYENACC_PE_NPE_IMEM;
        return IX_SUCCESS;
    } /* end of if */

    if (IXP400_PARITYENACC_VAL_BIT_CHECK(
            ixParityENAccNpePEConfig[ixNpeId].npeParityErrorStatus.\
                npeStatusRegisterValue, (UINT32) IXP400_PARITYENACC_NPE_STATUS_DMEM_PARITY))
    {
        ixNpePECMsg->npeParitySource = IXP400_PARITYENACC_PE_NPE_DMEM;
        return IX_SUCCESS;
    } /* end of if */

    if (IXP400_PARITYENACC_VAL_BIT_CHECK(
            ixParityENAccNpePEConfig[ixNpeId].npeParityErrorStatus.\
                npeStatusRegisterValue, (UINT32) IXP400_PARITYENACC_NPE_STATUS_EXT_ERROR))
    {
        ixNpePECMsg->npeParitySource = IXP400_PARITYENACC_PE_NPE_EXT;
        return IX_SUCCESS;
    } /* end of if */

#ifndef NDEBUG
    IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR,
        "ixParityENAccNpePEParityErrorContextFetch(): "\
        "Can't fetch parity context of NPE #%u!!!\n", ixNpeId, 0,0,0,0,0);
#endif /* end of #ifndef NDEBUG */
    return IX_FAIL;
} /* end of ixParityENAccNpePEParityErrorContextFetch() function */


IX_STATUS
ixParityENAccNpePEParityInterruptClear (IxParityENAccPENpeId ixNpeId)
{
    /* Validate parameters */
    if (ixNpeId >= IXP400_PARITYENACC_PE_NPE_MAX)
    {
        return IX_FAIL;
    } /* end of if */

    /* Disable the interrupt from triggering further */
    return ixParityENAccIcInterruptDisable(
               (IXP400_PARITYENACC_PE_NPE_A == ixNpeId) ? 
                IXP400_PARITYENACC_INTC_NPEA_PARITY_INTERRUPT : 
               (IXP400_PARITYENACC_PE_NPE_B == ixNpeId) ?
                IXP400_PARITYENACC_INTC_NPEB_PARITY_INTERRUPT : 
                IXP400_PARITYENACC_INTC_NPEC_PARITY_INTERRUPT);
} /* end of ixParityENAccNpePEParityInterruptClear() function */

void
ixParityENAccNpePEParityErrorStatusGet (void)
{
    /* Local Variables */
    IxParityENAccPENpeId ixNpeId = IXP400_PARITYENACC_PE_NPE_A;

    /*
     * Read the raw parity error status into local data structure
     * from the control and status registers of all the NPEs
     */
    for (; ixNpeId < IXP400_PARITYENACC_PE_NPE_MAX; ixNpeId++)
    {
        IXP400_PARITYENACC_REG_READ(
            ixParityENAccNpePEConfig[ixNpeId].npePERegisters.npeControlRegister,
            &ixParityENAccNpePEConfig[ixNpeId].npeParityErrorStatus.\
                npeControlRegisterValue);
        IXP400_PARITYENACC_REG_READ(
            ixParityENAccNpePEConfig[ixNpeId].npePERegisters.npeStatusRegister,
            &ixParityENAccNpePEConfig[ixNpeId].npeParityErrorStatus.\
                npeStatusRegisterValue);
    } /* end of for */
} /* end of ixParityENAccNpePEParityErrorStatusGet() function */

/*
 * Local functions definitions.
 */

void
ixParityENAccNpePENpeAIsr(void)
{
    /*
     * No need to read the parity error status in the ISR.
     *
     * Invoke the internal NPE - A callback routine to notify the
     * pairty error detected in IMEM/DMEM/ExtErr.
     * 
     * NOTE: The NPE parity error context information will be 
     * obtained only when the public API client application
     * requests for such information.
     */
    (*ixParityENAccNpePEConfig[IXP400_PARITYENACC_PE_NPE_A].npePECallback)(
        ixParityENAccNpePEConfig[IXP400_PARITYENACC_PE_NPE_A].npeIsrInfo.npeInterruptId,
        ixParityENAccNpePEConfig[IXP400_PARITYENACC_PE_NPE_A].npeIsrInfo.npeIsr);
} /* end of ixParityENAccNpePENpeAIsr() function */

void
ixParityENAccNpePENpeBIsr(void)
{
    /*
     * No need to read the parity error status in the ISR.
     *
     * Invoke the internal NPE - B callback routine to notify the
     * pairty error detected in IMEM/DMEM/ExtErr.
     * 
     * NOTE: The NPE parity error context information will be 
     * obtained only when the public API client application
     * requests for such information.
     */
    (*ixParityENAccNpePEConfig[IXP400_PARITYENACC_PE_NPE_B].npePECallback)(
        ixParityENAccNpePEConfig[IXP400_PARITYENACC_PE_NPE_B].npeIsrInfo.npeInterruptId,
        ixParityENAccNpePEConfig[IXP400_PARITYENACC_PE_NPE_B].npeIsrInfo.npeIsr);

    return;
} /* end of ixParityENAccNpePENpeBIsr() function */

void
ixParityENAccNpePENpeCIsr(void)
{
    /*
     * No need to read the parity error status in the ISR.
     *
     * Invoke the internal NPE - C callback routine to notify the
     * pairty error detected in IMEM/DMEM/ExtErr.
     * 
     * NOTE: The NPE parity error context information will be 
     * obtained only when the public API client application
     * requests for such information.
     */
    (*ixParityENAccNpePEConfig[IXP400_PARITYENACC_PE_NPE_C].npePECallback)(
        ixParityENAccNpePEConfig[IXP400_PARITYENACC_PE_NPE_C].npeIsrInfo.npeInterruptId,
        ixParityENAccNpePEConfig[IXP400_PARITYENACC_PE_NPE_C].npeIsrInfo.npeIsr);

    return;
} /* end of ixParityENAccNpePENpeCIsr() function */

#endif /* __ixp46X */