ixparityenaccnpepe.c

有关ARM开发板上的IXP400网络驱动程序的源码以。

/**
 * @file IxParityENAccNpePE.c
 *
 * @author Intel Corporation
 * @date 26 July 2004
 *
 * @brief  Source file for NPE Parity Detection Enabler sub-component 
 * of the IXP400 Parity Error Notifier access component.
 *
 * @par
 * IXP400 SW Release version 2.1
 * 
 * -- Copyright Notice --
 * 
 * @par
 * Copyright (c) 2001-2005, Intel Corporation.
 * All rights reserved.
 * 
 * @par
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 
 * 
 * @par
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * 
 * @par
 * -- End of Copyright Notice --
 */

#ifdef __ixp46X

/* 
 * System defined include files
 */
#include "IxOsal.h"

/*
 * User defined include files
 *
 * NOTE: The NPE headerfiles must appear in that order
 */
#include "IxParityENAccIcE.h"
#include "IxParityENAccNpePE.h"
#include "IxParityENAccNpePE_p.h"

/*
 * NPE sub-module level functions definitions
 */

IX_STATUS
ixParityENAccNpePEInit (IxParityENAccInternalCallback ixNpePECallback)
{
    UINT32 npeAVirtualBaseAddr = 0;
    UINT32 npeBVirtualBaseAddr = 0;
    UINT32 npeCVirtualBaseAddr = 0;
    UINT32 ebcVirtualBaseAddr  = 0;
    UINT32 ebcConfigReg1Value  = 0;

    /*
     * These Bits are to be combined always with the Parity Error Detection 
     * configuration bits.  Otherwise their effect is Nullified
     */
    UINT32 npePDCfgFlags  = IXP400_PARITYENACC_NPE_CONTROL_IPEWE | 
                            IXP400_PARITYENACC_NPE_CONTROL_DPEWE |
                            IXP400_PARITYENACC_NPE_CONTROL_EEEWE;
    UINT32 npePDCfgStatus = 0;

    register IxParityENAccNpePEConfig *npeAPEConfig = 
        &ixParityENAccNpePEConfig[IXP400_PARITYENACC_PE_NPE_A];
    register IxParityENAccNpePEConfig *npeBPEConfig = 
        &ixParityENAccNpePEConfig[IXP400_PARITYENACC_PE_NPE_B];
    register IxParityENAccNpePEConfig *npeCPEConfig = 
        &ixParityENAccNpePEConfig[IXP400_PARITYENACC_PE_NPE_C];

    /* Verify parameters */
    if ((IxParityENAccInternalCallback)NULL == ixNpePECallback)
    {

        return IX_FAIL;
    } /* end of if */

    /* Memory mapping of the NPE-A registers */
    if ((UINT32)NULL == (npeAVirtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP (
                                                IXP400_PARITYENACC_NPEA_BASEADDR,
                                                IXP400_PARITYENACC_NPE_MEMMAP_SIZE)))
    {
        return IX_FAIL;
    } /* end of if */

    /* Memory mapping of the NPE-B registers */
    if ((UINT32)NULL == (npeBVirtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP (
                                                IXP400_PARITYENACC_NPEB_BASEADDR,
                                                IXP400_PARITYENACC_NPE_MEMMAP_SIZE)))
    {
        IX_OSAL_MEM_UNMAP(npeAVirtualBaseAddr);
        return IX_FAIL;
    } /* end of if */

    /* Memory mapping of the NPE-C registers */
    if ((UINT32)NULL == (npeCVirtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP (
                                                IXP400_PARITYENACC_NPEC_BASEADDR,
                                                IXP400_PARITYENACC_NPE_MEMMAP_SIZE)))
    {
        IX_OSAL_MEM_UNMAP(npeAVirtualBaseAddr);
        IX_OSAL_MEM_UNMAP(npeBVirtualBaseAddr);
        return IX_FAIL;
    } /* end of if */

    /* Memory mapping of the Expansion Bus Controller Config Register #1 */
    if ((UINT32)NULL == (ebcVirtualBaseAddr =  (UINT32) IX_OSAL_MEM_MAP (
                                                IXP400_PARITYENACC_EBC_BASEADDR,
                                                IXP400_PARITYENACC_EBC_MEMMAP_SIZE)))
    {
        IX_OSAL_MEM_UNMAP(npeAVirtualBaseAddr);
        IX_OSAL_MEM_UNMAP(npeBVirtualBaseAddr);
        IX_OSAL_MEM_UNMAP(npeCVirtualBaseAddr);
        return IX_FAIL;
    } /* end of if */


    /* 
     * Fetch the NPE Error Handling Enable Status from Expansion Bus Controller
     * Config Register #1
     */

    /* Enable the NPE Error Handling Bits for Parity Error Interrupt Generation for EXT ERR */
    IXP400_PARITYENACC_REG_BIT_SET(ebcVirtualBaseAddr, IXP400_PARITYENACC_NPE_EXPCNFG1_NPEA_ERREN);
    IXP400_PARITYENACC_REG_BIT_SET(ebcVirtualBaseAddr, IXP400_PARITYENACC_NPE_EXPCNFG1_NPEB_ERREN);
    IXP400_PARITYENACC_REG_BIT_SET(ebcVirtualBaseAddr, IXP400_PARITYENACC_NPE_EXPCNFG1_NPEC_ERREN);

    IXP400_PARITYENACC_REG_READ(ebcVirtualBaseAddr, &ebcConfigReg1Value);

    ixParityENAccNpePEErrorHandlingEnable[IXP400_PARITYENACC_PE_NPE_A] = 
        IXP400_PARITYENACC_VAL_BIT_CHECK(ebcConfigReg1Value,
            IXP400_PARITYENACC_NPE_EXPCNFG1_NPEA_ERREN);

    ixParityENAccNpePEErrorHandlingEnable[IXP400_PARITYENACC_PE_NPE_B] = 
        IXP400_PARITYENACC_VAL_BIT_CHECK(ebcConfigReg1Value,
            IXP400_PARITYENACC_NPE_EXPCNFG1_NPEB_ERREN);

    ixParityENAccNpePEErrorHandlingEnable[IXP400_PARITYENACC_PE_NPE_C] = 
        IXP400_PARITYENACC_VAL_BIT_CHECK(ebcConfigReg1Value,
            IXP400_PARITYENACC_NPE_EXPCNFG1_NPEC_ERREN);

    /* Virtual Addresses assignment for NPE-A/B/C Registers */
    npeAPEConfig->npePERegisters.npeStatusRegister  = 
        npeAVirtualBaseAddr + IXP400_PARITYENACC_NPE_STATUS_OFFSET;
    npeAPEConfig->npePERegisters.npeControlRegister = 
        npeAVirtualBaseAddr + IXP400_PARITYENACC_NPE_CONTROL_OFFSET;

    npeBPEConfig->npePERegisters.npeStatusRegister  = 
        npeBVirtualBaseAddr + IXP400_PARITYENACC_NPE_STATUS_OFFSET;
    npeBPEConfig->npePERegisters.npeControlRegister = 
        npeBVirtualBaseAddr + IXP400_PARITYENACC_NPE_CONTROL_OFFSET;

    npeCPEConfig->npePERegisters.npeStatusRegister  = 
        npeCVirtualBaseAddr + IXP400_PARITYENACC_NPE_STATUS_OFFSET;
    npeCPEConfig->npePERegisters.npeControlRegister = 
        npeCVirtualBaseAddr + IXP400_PARITYENACC_NPE_CONTROL_OFFSET;

    /* Register main module internal callback routines for NPEs */
    npeAPEConfig->npePECallback = ixNpePECallback;
    npeBPEConfig->npePECallback = ixNpePECallback;
    npeCPEConfig->npePECallback = ixNpePECallback;

    /* Interrupt Service Routine(s) Info for NPEs */
    npeAPEConfig->npeIsrInfo.npeInterruptId = IRQ_IXP400_INTC_PARITYENACC_NPEA;
    npeAPEConfig->npeIsrInfo.npeIsr = ixParityENAccNpePENpeAIsr;

    npeBPEConfig->npeIsrInfo.npeInterruptId = IRQ_IXP400_INTC_PARITYENACC_NPEB;
    npeBPEConfig->npeIsrInfo.npeIsr = ixParityENAccNpePENpeBIsr;

    npeCPEConfig->npeIsrInfo.npeInterruptId = IRQ_IXP400_INTC_PARITYENACC_NPEC;
    npeCPEConfig->npeIsrInfo.npeIsr = ixParityENAccNpePENpeCIsr;

    /*
     * Disable parity error detection for the IMEM, DMEM and Ext Error 
     * of all the NPEs
     */

    /* 
     * Enable the Write Enable Bits to clear off IMEM, DMEM & Ext Error bits
     */
    IXP400_PARITYENACC_REG_READ(npeAPEConfig->npePERegisters.npeControlRegister, &npePDCfgStatus);

    IXP400_PARITYENACC_VAL_BIT_SET(npePDCfgStatus, npePDCfgFlags);
    IXP400_PARITYENACC_VAL_BIT_CLEAR(npePDCfgStatus, IXP400_PARITYENACC_NPE_CONTROL_IPE |
        IXP400_PARITYENACC_NPE_CONTROL_DPE | IXP400_PARITYENACC_NPE_CONTROL_EEE);

    IXP400_PARITYENACC_REG_BIT_SET(npeAPEConfig->npePERegisters.npeControlRegister, npePDCfgStatus);


    IXP400_PARITYENACC_REG_READ(npeBPEConfig->npePERegisters.npeControlRegister, &npePDCfgStatus);

    IXP400_PARITYENACC_VAL_BIT_SET(npePDCfgStatus, npePDCfgFlags);
    IXP400_PARITYENACC_VAL_BIT_CLEAR(npePDCfgStatus, IXP400_PARITYENACC_NPE_CONTROL_IPE |
        IXP400_PARITYENACC_NPE_CONTROL_DPE | IXP400_PARITYENACC_NPE_CONTROL_EEE);

    IXP400_PARITYENACC_REG_BIT_SET(npeBPEConfig->npePERegisters.npeControlRegister, npePDCfgStatus);


    IXP400_PARITYENACC_REG_READ(npeCPEConfig->npePERegisters.npeControlRegister, &npePDCfgStatus);

    IXP400_PARITYENACC_VAL_BIT_SET(npePDCfgStatus, npePDCfgFlags);
    IXP400_PARITYENACC_VAL_BIT_CLEAR(npePDCfgStatus, IXP400_PARITYENACC_NPE_CONTROL_IPE |
        IXP400_PARITYENACC_NPE_CONTROL_DPE | IXP400_PARITYENACC_NPE_CONTROL_EEE);

    IXP400_PARITYENACC_REG_BIT_SET(npeCPEConfig->npePERegisters.npeControlRegister, npePDCfgStatus);

    /* Install NPE-A/B/C Interrupt Service Routines */
    {
        INT32 lockKey = ixOsalIrqLock();
        if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_NPEA,
                            (IxOsalVoidFnVoidPtr) ixParityENAccNpePENpeAIsr, (void *) NULL)) ||
            (IX_FAIL == ixParityENAccIcInterruptDisable(
                            IXP400_PARITYENACC_INTC_NPEA_PARITY_INTERRUPT)))
        {
            ixOsalIrqUnlock(lockKey);
            IX_OSAL_MEM_UNMAP(npeAVirtualBaseAddr);
            IX_OSAL_MEM_UNMAP(npeBVirtualBaseAddr);
            IX_OSAL_MEM_UNMAP(npeCVirtualBaseAddr);
            IX_OSAL_MEM_UNMAP(ebcVirtualBaseAddr);
            return IX_FAIL;
        } /* end of if */

        if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_NPEB,
                            (IxOsalVoidFnVoidPtr) ixParityENAccNpePENpeBIsr, (void *) NULL)) ||
            (IX_FAIL == ixParityENAccIcInterruptDisable(
                            IXP400_PARITYENACC_INTC_NPEB_PARITY_INTERRUPT)))
        {
            ixOsalIrqUnbind((UINT32) IRQ_IXP400_INTC_PARITYENACC_NPEA);

            ixOsalIrqUnlock(lockKey);
            IX_OSAL_MEM_UNMAP(npeAVirtualBaseAddr);
            IX_OSAL_MEM_UNMAP(npeBVirtualBaseAddr);
            IX_OSAL_MEM_UNMAP(npeCVirtualBaseAddr);
            IX_OSAL_MEM_UNMAP(ebcVirtualBaseAddr);
            return IX_FAIL;
        } /* end of if */

        if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_NPEC,
                            (IxOsalVoidFnVoidPtr) ixParityENAccNpePENpeCIsr, (void *) NULL))||
            (IX_FAIL == ixParityENAccIcInterruptDisable(
                            IXP400_PARITYENACC_INTC_NPEC_PARITY_INTERRUPT)))
        {
            ixOsalIrqUnbind((UINT32) IRQ_IXP400_INTC_PARITYENACC_NPEA);
            ixOsalIrqUnbind((UINT32) IRQ_IXP400_INTC_PARITYENACC_NPEB);

            ixOsalIrqUnlock(lockKey);
            IX_OSAL_MEM_UNMAP(npeAVirtualBaseAddr);
            IX_OSAL_MEM_UNMAP(npeBVirtualBaseAddr);
            IX_OSAL_MEM_UNMAP(npeCVirtualBaseAddr);
            IX_OSAL_MEM_UNMAP(ebcVirtualBaseAddr);
            return IX_FAIL;
        } /* end of if */
        ixOsalIrqUnlock(lockKey);
    }

    return IX_SUCCESS;
} /* end of ixParityENAccNpePEInit() function */

IX_STATUS
ixParityENAccNpePEDetectionConfigure (
    IxParityENAccPENpeId ixNpeId,
    IxParityENAccNpePEConfigOption ixNpePDCfg)
{
    UINT32 npePDCfgFlags  = IXP400_PARITYENACC_NPE_CONTROL_IPE |
                            IXP400_PARITYENACC_NPE_CONTROL_DPE |
                            IXP400_PARITYENACC_NPE_CONTROL_EEE ;