ixparityenaccmcupe.c

有关ARM开发板上的IXP400网络驱动程序的源码以。

     *  v
     *
     * While: -   No parity error
     *        O   Overflow of parity errors
     *        S   Single bit parity error
     *        M   Multibit parity error
     *        0   Parity error #0
     *        1   Parity error #1
     *        (n) Parity error reporting/notification order
     */

    /* Parity Error Not Set (Row #1 & Column #1) */
    if ((FALSE == mcuParityError0) && (FALSE == mcuParityError1))
    {
        /* No Parity Errors? */
        if (FALSE == mcuParityErrorN)
        {
            ixMcuPECMsg->mcuParitySource = IXP400_PARITYENACC_PE_MCU_NOPARITY;
            return IX_SUCCESS;
        } /* else of if */
        /* Overflow of Parity Errors
         *
         * This scenario occurs after clearing the other multi/single-bit
         * parity errors and the Overflow of parity errors have been observed
         *
         * NOTE: Other Parity Error Context attributes will have undetermined
         *       values
         */
        else
        {
            ixMcuPECMsg->mcuParitySource = IXP400_PARITYENACC_PE_MCU_OVERFLOW;
            return IX_SUCCESS;
        } /* end of if */
    } /* end of if */

    /*
     * Retrieve Parity Error #1
     *
     * Case-A: Parity Error #1 is multi-bit  (AND) Parity Error #0 is single-bit
     * i.e., (Notification #4) (OR)
     * Case-B: Parity Error #1 is multi-bit  (AND) Parity Error #0 not Set
     * i.e., (Notification #5) (OR)  
     * Case-C: Parity Error #1 is single-bit (AND) Parity Error #0 not Set
     * i.e., (Notification #8)
     */
    if ((TRUE == mcuParityError1) && 
        /* Case - A */
        (((IXP400_PARITYENACC_MCU_ERR_SMBIT_MLT == mcuParitySource1) &&
         (((TRUE == mcuParityError0) && 
           (IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL == mcuParitySource0)) ||
        /* Case - B */
          (FALSE == mcuParityError0))) ||
        /* Case - C */
        ((IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL == mcuParitySource1) &&
         (FALSE == mcuParityError0))))
    {
        ixParityENAccMcuPEParityErrorStatusTransform (ixMcuPECMsg,
        ixParityENAccMcuPEConfig.mcuParityErrorStatus.mcuElog1Value,
            ixParityENAccMcuPEConfig.mcuParityErrorStatus.mcuEcar1Value);

        return IX_SUCCESS;
    } /* end of if */

    /* 
     * All other cases where Parity Error #0 will be retrieved
     */
    ixParityENAccMcuPEParityErrorStatusTransform (ixMcuPECMsg,
        ixParityENAccMcuPEConfig.mcuParityErrorStatus.mcuElog0Value,
        ixParityENAccMcuPEConfig.mcuParityErrorStatus.mcuEcar0Value);

    return IX_SUCCESS;
} /* end of ixParityENAccMcuPEParityErrorContextFetch() function */

IX_STATUS
ixParityENAccMcuPEParityInterruptClear (
    IxParityENAccMcuPEParityErrorSource ixMcuParityErrSrc,
    IxParityENAccPEParityErrorAddress ixMcuParityErrAddress)
{
    BOOL mcuParityError0 = FALSE;
    BOOL mcuParityError1 = FALSE;
    BOOL mcuParityErrorN = FALSE;

    UINT32 mcuParitySource0 = IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL;
    UINT32 mcuParitySource1 = IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL;

    register IxParityENAccMcuPERegisters *mcuPERegisters = 
                &ixParityENAccMcuPEConfig.mcuPERegisters;

    IxParityENAccPEParityErrorAddress mcuParityErrorAddr = 
        IXP400_PARITYENACC_VAL_READ(ixParityENAccMcuPEConfig.\
            mcuParityErrorStatus.mcuEcar0Value, IXP400_PARITYENACC_MCU_ERR_ADDRESS_MASK);

    /* Identify the Multi & Single bit parity errors */
    ixParityENAccMcuPEParityErrorStatusInterpret (
        &mcuParityError0, &mcuParityError1, &mcuParityErrorN,
        &mcuParitySource0, &mcuParitySource1);

    switch (ixMcuParityErrSrc)
    {
        case IXP400_PARITYENACC_PE_MCU_SBIT:
        {
            /* Parity error number #0 is of single bit type */
            if ((TRUE == mcuParityError0) && 
                (IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL == mcuParitySource0) &&
                (mcuParityErrorAddr == ixMcuParityErrAddress))
            {
                /* Write '1' to clear the single bit parity interrupt */
                IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
                    IXP400_PARITYENACC_MCU_ERROR0_MASK);
                break;
            } /* end of if */
            
            /* Parity error number #1 is of single bit type */
    
            /* Write '1' to clear the single bit parity interrupt */
            IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
                IXP400_PARITYENACC_MCU_ERROR1_MASK);
            break;
        } /* end of case IXP400_PARITYENACC_PE_MCU_SBIT */

        case IXP400_PARITYENACC_PE_MCU_MBIT:
        {
            /* Parity error number #0 is of multi bit type */
            if ((TRUE == mcuParityError0) && 
                (IXP400_PARITYENACC_MCU_ERR_SMBIT_MLT == mcuParitySource0) &&
                (mcuParityErrorAddr == ixMcuParityErrAddress))
            {
                /* Write '1' to clear the multi bit parity interrupt */
                IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
                    IXP400_PARITYENACC_MCU_ERROR0_MASK);
                break;
            } /* end of if */
            
            /* Parity error number #1 is of multi bit type */
    
            /* Write '1' to clear the multi bit parity interrupt */
            IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
                IXP400_PARITYENACC_MCU_ERROR1_MASK);
            break;
        } /* end of case IXP400_PARITYENACC_PE_MCU_MBIT */

        case IXP400_PARITYENACC_PE_MCU_OVERFLOW:
        {
            /* Write '1' to clear the Parity Overflow Interrupt */
            IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
                IXP400_PARITYENACC_MCU_ERRORN_MASK);
            break;
        } /* end of case IXP400_PARITYENACC_PE_MCU_OVERFLOW */
        default:
        {
            /* This part of the code should never be reached */
            IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR,
                "ixParityENAccMcuPEParityInterruptClear(): "
                "Invalid MCU interrupt source to clear\n", 0,0,0,0,0,0);
            return IX_FAIL;
        } /* end of case default */
    } /* end of switch */

    return IX_SUCCESS;
} /* end of ixParityENAccMcuPEParityInterruptClear() function */

void
ixParityENAccMcuPEIsr (void)
{
    /*
     * No need to read the ECC/parity error status in the ISR
     * Invoke the internal MCU callback routine to notify the
     * ECC/pairty error detected.
     * 
     * NOTE: The ECC/parity error context information will be 
     * obtained only when the public API client application
     * requests for such information.
     */
    (*ixParityENAccMcuPEConfig.mcuPECallback)(
        ixParityENAccMcuPEConfig.mcuIsrInfo.mcuInterruptId,
        ixParityENAccMcuPEConfig.mcuIsrInfo.mcuIsr);
} /* end of ixParityENAccMcuPEIsr() function */

void
ixParityENAccMcuPEParityErrorStatusGet (void)
{
    register IxParityENAccMcuPERegisters *mcuPERegisters = 
                &ixParityENAccMcuPEConfig.mcuPERegisters;
    register IxParityENAccMcuPEParityErrorStatus *mcuPEStatus = 
                &ixParityENAccMcuPEConfig.mcuParityErrorStatus;
    /*
     * Read the raw parity error status into local datastructure
     * from the various MCU registers
     */

    /* ECC Control Register contents */
    IXP400_PARITYENACC_REG_READ(mcuPERegisters->mcuEccr, &mcuPEStatus->mcuEccrValue);

    /* ECC Log Register_0 contents */
    IXP400_PARITYENACC_REG_READ(mcuPERegisters->mcuElog0, &mcuPEStatus->mcuElog0Value);
    
    /* ECC Log Register_1 contents */
    IXP400_PARITYENACC_REG_READ(mcuPERegisters->mcuElog1, &mcuPEStatus->mcuElog1Value);

    /* ECC Address Register_0 contents */
    IXP400_PARITYENACC_REG_READ(mcuPERegisters->mcuEcar0, &mcuPEStatus->mcuEcar0Value);

    /* ECC Address Register_1 contents */
    IXP400_PARITYENACC_REG_READ(mcuPERegisters->mcuEcar1, &mcuPEStatus->mcuEcar1Value);

    /* Memory Controller Interrupt Status Register contents */
    IXP400_PARITYENACC_REG_READ(mcuPERegisters->mcuMcisr, &mcuPEStatus->mcuMcisrValue);
} /* end of ixParityENAccMcuPEParityErrorStatusGet() function */

void
ixParityENAccMcuPEParityErrorStatusTransform (
    IxParityENAccMcuPEParityErrorContext *ixMcuPECMsg,
    UINT32 mcuElogNValue,
    UINT32 mcuEcarNValue)
{
    /*
     * Input parameter validation is not done in the local functions 
     * to avoid extra code.
     */

        /* ECC/parity error is of Single or Multi bit type */
        ixMcuPECMsg->mcuParitySource = 
            (IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL == 
             IXP400_PARITYENACC_VAL_READ(mcuElogNValue,
                 IXP400_PARITYENACC_MCU_ERR_SMBIT_MASK)) ? 
             IXP400_PARITYENACC_PE_MCU_SBIT : IXP400_PARITYENACC_PE_MCU_MBIT;

        /* Identify Read or Write access that has caused parity error */
        ixMcuPECMsg->mcuAccessType =
            (IXP400_PARITYENACC_MCU_ERR_RW_READ == 
             IXP400_PARITYENACC_VAL_READ(mcuElogNValue,
                 IXP400_PARITYENACC_MCU_ERR_RW_MASK)) ?
                     IXP400_PARITYENACC_PE_READ : IXP400_PARITYENACC_PE_WRITE;

        /* Fetch the parity error syndrome */
        ixMcuPECMsg->mcuParityData = (IxParityENAccPEParityErrorData)
             IXP400_PARITYENACC_VAL_READ(mcuElogNValue,
                 IXP400_PARITYENACC_MCU_ERR_SYNDROME_MASK);

        /* Identify the requesting interface to the MCU */
        ixMcuPECMsg->mcuRequester = 
            (IXP400_PARITYENACC_MCU_ERR_MASTER_CORE_BIU == 
             IXP400_PARITYENACC_VAL_READ(mcuElogNValue,
                 IXP400_PARITYENACC_MCU_ERR_MASTER_MASK)) ?
                     IXP400_PARITYENACC_PE_MCU_MPI : IXP400_PARITYENACC_PE_MCU_AHB_BUS;

        /* Feth the parity error address */
        ixMcuPECMsg->mcuParityAddress = (IxParityENAccPEParityErrorAddress)
            IXP400_PARITYENACC_VAL_READ(mcuEcarNValue,
                IXP400_PARITYENACC_MCU_ERR_ADDRESS_MASK);
} /* end of ixParityENAccMcuPEParityErrorStatusTransform() function */

#endif /* __ixp46X */