ixparityenaccmcupe.c

有关ARM开发板上的IXP400网络驱动程序的源码以。

/**
 * @file IxParityENAccMcuPE.c
 *
 * @author Intel Corporation
 * @date 26 July 2004
 *
 * @brief Source file for MCU Parity Detection Enabler sub-component 
 * of the IXP400 Parity Error Notifier access component.
 *
 * @par
 * IXP400 SW Release version 2.1
 * 
 * -- Copyright Notice --
 * 
 * @par
 * Copyright (c) 2001-2005, Intel Corporation.
 * All rights reserved.
 * 
 * @par
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 
 * 
 * @par
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * 
 * @par
 * -- End of Copyright Notice --
 */

#ifdef __ixp46X

/* 
 * System defined include files
 */
#include "IxOsal.h"

/*
 * User defined include files
 */
#include "IxParityENAccIcE.h"
#include "IxParityENAccMcuPE.h"
#include "IxParityENAccMcuPE_p.h"

/*
 * MCU Sub-module level functions definitions
 */

IX_STATUS
ixParityENAccMcuPEInit (IxParityENAccInternalCallback ixMcuPECallback)
{
    UINT32 virtualBaseAddr = 0;

    /* Verify parameters */
    if ((IxParityENAccInternalCallback)NULL == ixMcuPECallback)
    {
        return IX_FAIL;
    } /* end of if */

    /* Memory mapping of the MCU registers */
    if ((UINT32)NULL == (virtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP (
                                            IXP400_PARITYENACC_MCU_BASEADDR,
                                            IXP400_PARITYENACC_MCU_MEMMAP_SIZE)))
    {
        return IX_FAIL;
    } /* end of if */

    /* Virtual Addresses assignment for MCU Registers */
    ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr  = 
        virtualBaseAddr + IXP400_PARITYENACC_MCU_ECCR_OFFSET;
    ixParityENAccMcuPEConfig.mcuPERegisters.mcuElog0 = 
        virtualBaseAddr + IXP400_PARITYENACC_MCU_ELOG0_OFFSET;
    ixParityENAccMcuPEConfig.mcuPERegisters.mcuElog1 = 
        virtualBaseAddr + IXP400_PARITYENACC_MCU_ELOG1_OFFSET;
    ixParityENAccMcuPEConfig.mcuPERegisters.mcuEcar0 = 
        virtualBaseAddr + IXP400_PARITYENACC_MCU_ECAR0_OFFSET;
    ixParityENAccMcuPEConfig.mcuPERegisters.mcuEcar1 = 
        virtualBaseAddr + IXP400_PARITYENACC_MCU_ECAR1_OFFSET;
    ixParityENAccMcuPEConfig.mcuPERegisters.mcuMcisr = 
        virtualBaseAddr + IXP400_PARITYENACC_MCU_MCISR_OFFSET;

    /* Register main module internal callback routine */
    ixParityENAccMcuPEConfig.mcuPECallback = ixMcuPECallback;

    /* Interrupt Service Routine Info for debug purpose only */
    ixParityENAccMcuPEConfig.mcuIsrInfo.mcuInterruptId = 
        IRQ_IXP400_INTC_PARITYENACC_MCU;
    ixParityENAccMcuPEConfig.mcuIsrInfo.mcuIsr = ixParityENAccMcuPEIsr;

    /*
     * Disable parity error detection for both single and multi-bit ECC
     * and correction of single bit parity using ECC
     */
    IXP400_PARITYENACC_REG_BIT_CLEAR(
        ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr,
        IXP400_PARITYENACC_MCU_SBIT_CORRECT_MASK |
        IXP400_PARITYENACC_MCU_MBIT_REPORT_MASK  |
        IXP400_PARITYENACC_MCU_SBIT_REPORT_MASK);

    /* Clear off the pending interrupts, if any */
    IXP400_PARITYENACC_REG_BIT_SET(
        ixParityENAccMcuPEConfig.mcuPERegisters.mcuMcisr,
        IXP400_PARITYENACC_MCU_ERROR0_MASK |
        IXP400_PARITYENACC_MCU_ERROR1_MASK |
        IXP400_PARITYENACC_MCU_ERRORN_MASK);

    /* Install MCU Interrupt Service Routine after disabling the interrupt */
    {
        INT32 lockKey = ixOsalIrqLock();
        if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_MCU,
                                        (IxOsalVoidFnVoidPtr) ixParityENAccMcuPEIsr,
                                        (void *) NULL)) ||
            (IX_SUCCESS != ixParityENAccIcInterruptDisable(
                            IXP400_PARITYENACC_INTC_MCU_PARITY_INTERRUPT)))
        {
            ixOsalIrqUnlock(lockKey);
            IX_OSAL_MEM_UNMAP (virtualBaseAddr);
            return IX_FAIL;
        } /* end of if */
        ixOsalIrqUnlock(lockKey);
    }
    return IX_SUCCESS;
} /* end of ixParityENAccMcuPEInit() function */

IX_STATUS 
ixParityENAccMcuPEDetectionConfigure (IxParityENAccMcuPEConfigOption ixMcuPDCfg)
{
    UINT32 mcuPDCfgFlags  = IXP400_PARITYENACC_MCU_ECC_EN_MASK; /* Always to be included */
    UINT32 mcuPDCfgStatus = 0;
    UINT32 mcuTmpPDCfgStatus = 0;

    /*
     * Enable parity error detection for given options
     *
     * - ECC enable
     * - Single-bit ECC error report
     * - Multi-bit ECC error report
     * - Single-bit parity correction using ECC
     */

    /* Enable Single-bit parity error detection */
    if (IXP400_PARITYENACC_PE_ENABLE == ixMcuPDCfg.singlebitDetectEnabled)
    {
        mcuPDCfgFlags |= IXP400_PARITYENACC_MCU_SBIT_REPORT_MASK;
    } /* end of if */

    /* Enable Single-bit parity error correction */
    if (IXP400_PARITYENACC_PE_ENABLE == ixMcuPDCfg.singlebitCorrectionEnabled)
    {
        mcuPDCfgFlags |= IXP400_PARITYENACC_MCU_SBIT_CORRECT_MASK;
    } /* end of if */

    /* Enable Multi-bit parity error detection */
    if (IXP400_PARITYENACC_PE_ENABLE == ixMcuPDCfg.multibitDetectionEnabled)
    {
        mcuPDCfgFlags |= IXP400_PARITYENACC_MCU_MBIT_REPORT_MASK;
    } /* end of if */

    /* Check the current ECC feature configuration */
    IXP400_PARITYENACC_REG_READ(ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr,
        &mcuPDCfgStatus);

    /* Existing configuration is same as requested one */
    if (mcuPDCfgStatus == mcuPDCfgFlags)
    {
        return IX_SUCCESS;
    }
    mcuPDCfgStatus = mcuPDCfgFlags;

    IXP400_PARITYENACC_REG_WRITE((ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr),
        mcuPDCfgStatus);

    /* Verify that configuration has been successful or not */
    IXP400_PARITYENACC_REG_READ((ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr),
        &mcuTmpPDCfgStatus);

    if (mcuTmpPDCfgStatus == mcuPDCfgStatus)
    {
        /* Enable/Disable the corresponding interrupt at Interrupt Controller */
        IXP400_PARITYENACC_VAL_BIT_CLEAR(mcuPDCfgFlags,IXP400_PARITYENACC_MCU_ECC_EN_MASK);
        return (0 != mcuPDCfgFlags) ?
                        ixParityENAccIcInterruptEnable( 
                            IXP400_PARITYENACC_INTC_MCU_PARITY_INTERRUPT) :
                        ixParityENAccIcInterruptDisable(
                            IXP400_PARITYENACC_INTC_MCU_PARITY_INTERRUPT);
    }
    else
    {
        return IX_FAIL;
    } /* end of if */
} /* end of ixParityENAccMcuPEDetectionConfigure() function */

IX_STATUS 
ixParityENAccMcuPEParityErrorContextFetch (
    IxParityENAccMcuPEParityErrorContext *ixMcuPECMsg)
{
    BOOL mcuParityError0 = FALSE;
    BOOL mcuParityError1 = FALSE;
    BOOL mcuParityErrorN = FALSE;

    UINT32 mcuParitySource0 = IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL;
    UINT32 mcuParitySource1 = IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL;

    if ((IxParityENAccMcuPEParityErrorContext *)NULL == ixMcuPECMsg)
    {
        return IX_FAIL;
    } /* end of if */

    /* Fetch MCU registers' contents into internal datastructure */
    ixParityENAccMcuPEParityErrorStatusGet();

    /*
     * Prepare the Parity Error Context as needed by the Main sub-module
     */

    /* Identify the Multi & Single bit parity errors */
    ixParityENAccMcuPEParityErrorStatusInterpret ( &mcuParityError0, 
        &mcuParityError1, &mcuParityErrorN, &mcuParitySource0, &mcuParitySource1);

    /*
     * Select multi or single-bit parity errors as show in decision table
     *
     *        Parity #1 -->
     *
     *             -               S           M
     *  P     +------------+------------+------------+
     *  a  -  | -(10)/O(9) |    1 (8)   |    1 (5)   |
     *  r     +------------+------------+------------+
     *  i  S  |    0 (7)   |    0 (6)   |    1 (4)   |
     *  t     +------------+------------+------------+
     *  y  M  |    0 (3)   |    0 (2)   |    0 (1)   |
     *        +------------+------------+------------+
     *  #0
     *  |