ixtimesyncacc_p.h

有关ARM开发板上的IXP400网络驱动程序的源码以。

/**
 * @file IxTimeSyncAcc_p.h
 *
 * @author Intel Corporation
 * @date 29 November 2004
 *
 * @brief  Private header file for IXP400 Access Layer to IEEE 1588(TM)
 * Precision Clock Synchronisation Protocol Hardware Assist.
 *
 * @par
 * IXP400 SW Release version 2.1
 * 
 * -- Copyright Notice --
 * 
 * @par
 * Copyright (c) 2001-2005, Intel Corporation.
 * All rights reserved.
 * 
 * @par
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 
 * 
 * @par
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * 
 * @par
 * -- End of Copyright Notice --
 */

/*
 * #defines and macros used in this file.
 */

/* Inline or Non-Inlined function declaration/definition macro */
#ifdef NO_INLINE_APIS
    #define IXP400_TIMESYNCACC_INLINE  /* empty define */
#else /* else of ifdef NO_INLINE_APIS */
    #define IXP400_TIMESYNCACC_INLINE  __inline__
#endif /* end of ifdef NO_INLINE_APIS */

/*
 * SET, CLEAR & CHECK macros for bit manipulation on the 
 * memory mapped registers' contents
 */
#define IXP400_TIMESYNCACC_BIT_SET(regAddr, bitMask) \
do { \
    /* *(regAddr) |= (bitMask); */ \
    IX_OSAL_WRITE_LONG(regAddr, \
                       IX_OSAL_READ_LONG(regAddr) | bitMask); \
} while (0) /* Don't include ';' here */

#define IXP400_TIMESYNCACC_BIT_CLEAR(regAddr, bitMask) \
do { \
    /* *(regAddr) &= ~(bitMask); */ \
    IX_OSAL_WRITE_LONG(regAddr, \
                       IX_OSAL_READ_LONG(regAddr) & ~(bitMask)); \
} while (0) /* Don't include ';' here */

#define IXP400_TIMESYNCACC_BIT_SET_CHECK(regAddr, bitMask) \
    ((IX_OSAL_READ_LONG(regAddr)  & (bitMask)) == (bitMask))
/* Don't include ';' here */

/*
 * READ, WRITE macros for memory mapped registers
 */
#define IXP400_TIMESYNCACC_REG_READ(regAddr, varRef) \
do { \
    *(varRef) = IX_OSAL_READ_LONG(regAddr); \
} while (0) /* Don't include ';' here */

#define IXP400_TIMESYNCACC_REG_WRITE(regAddr, varValue) \
do { \
    IX_OSAL_WRITE_LONG(regAddr, varValue); \
} while (0) /* Don't include ';' here */

/* Masks to extract High and Low SHORTs from UINT32 values */
#define IXP400_TIMESYNCACC_MSB_SHORT_MASK  (0xFFFF0000)
#define IXP400_TIMESYNCACC_LSB_SHORT_MASK  (0x0000FFFF)

/* Location of SeqID in the register */
#define IXP400_TIMESYNCACC_SID_LOC         (16)

/* IRQ Level */
#define IRQ_IXP400_INTC_TSYNC IX_OSAL_IXP400_TSYNC_IRQ_LVL

/* Max Ports */
#define IXP400_TIMESYNCACC_MAX_1588PTP_PORT  (0x03)

/* Base Addresses for Block and Port Level Registers */
#define IXP400_TIMESYNCACC_BLREGS_BASEADDR   (0xC8010000)
#define IXP400_TIMESYNCACC_PLREGS_BASEADDR   (0xC8010040)

/* Size of the each Block / Port Level Register */
#define IXP400_TIMESYNCACC_BLPLREG_SIZE  (0x04)

/* Number of Block and Port Level Registers */
#define IXP400_TIMESYNCACC_BLREGS_COUNT  (0x10)
#define IXP400_TIMESYNCACC_PLREGS_COUNT  (0x08)

/* Address Ranges for Block and Port Level Registers */
#define IXP400_TIMESYNCACC_BLREGS_MEMMAP_SIZE  \
            (IXP400_TIMESYNCACC_BLPLREG_SIZE * \
             IXP400_TIMESYNCACC_BLREGS_COUNT)
#define IXP400_TIMESYNCACC_PLREGS_MEMMAP_SIZE  \
            (IXP400_TIMESYNCACC_BLPLREG_SIZE * \
             IXP400_TIMESYNCACC_PLREGS_COUNT * \
             IXP400_TIMESYNCACC_MAX_1588PTP_PORT)

/*
 * Block Level Registers Offset Values
 *
 * Please refer to the struct - IxTimeSyncAccBlockLevelRegisters defined
 * to hold the virtual addresses of the various block level registers of
 * time sync hardware 
 */
#define IXP400_TIMESYNCACC_TSC_OFFSET    (0x00)
#define IXP400_TIMESYNCACC_TSE_OFFSET    (0x04)
#define IXP400_TIMESYNCACC_ADD_OFFSET    (0x08)
#define IXP400_TIMESYNCACC_ACC_OFFSET    (0x0C)
/* TimeSync will not make use of the following four reserved registers but 
 * will be counted for correct implementation of offsets in the memory map
 *
 * Reserved for Testing
 * Reserved Unused
 * Reserved for NPE use
 * Reserved for NPE use
 */
#define IXP400_TIMESYNCACC_STL_OFFSET    (0x20)
#define IXP400_TIMESYNCACC_STH_OFFSET    (0x24)
#define IXP400_TIMESYNCACC_TTL_OFFSET    (0x28)
#define IXP400_TIMESYNCACC_TTH_OFFSET    (0x2C)
#define IXP400_TIMESYNCACC_ASSL_OFFSET   (0x30)
#define IXP400_TIMESYNCACC_ASSH_OFFSET   (0x34)
#define IXP400_TIMESYNCACC_AMSL_OFFSET   (0x38)
#define IXP400_TIMESYNCACC_AMSH_OFFSET   (0x3C)

/*
 * Port Level Registers Offset Values
 *
 * The following offset macros work as explained below.
 * 
 * Effective Address:= Starting Virtual Address + 
 *                     Vertical Offset + Block Offset for Port
 *
 * NOTE: a) Starting Virtual Address will be obtained using OSAL macro
 *       b) portNum (0 -> Max IXP400_TIMESYNCACC_MAX_1588PTP_PORT)
 *       c) Block Offset for Port starts from Zero
 *
 * The example assumes that Starting Virtual Address has been 0x40.
 *
 * Eg., CC0:  0x40 + (0x04 * 0x00) + (0x20 * 0x00) = 0x40
 *      XSH1: 0x40 + (0x04 * 0x03) + (0x20 * 0x01) = 0x6C
 *      RSH2: 0x40 + (0x04 * 0x05) + (0x20 * 0x02) = 0x94
 */

/* Vertical/Relative Offset of a given Port Level Register 
 * within a single set/block for each PTP Port
 *
 * Please refer to the struct - IxTimeSyncAccPortLevelRegisters defined
 * to hold the virtual addresses of the various block level registers of
 * time sync hardware
 */
#define IXP400_TIMESYNCACC_CC_VOFFSET     (0x00)
#define IXP400_TIMESYNCACC_CE_VOFFSET     (0x04)
#define IXP400_TIMESYNCACC_XSL_VOFFSET    (0x08)
#define IXP400_TIMESYNCACC_XSH_VOFFSET    (0x0C)
#define IXP400_TIMESYNCACC_RSL_VOFFSET    (0x10)
#define IXP400_TIMESYNCACC_RSH_VOFFSET    (0x14)
#define IXP400_TIMESYNCACC_UID_VOFFSET    (0x18)
#define IXP400_TIMESYNCACC_SID_VOFFSET    (0x1C)

/* Block wise offset of each Port Level Registers for a given PTP Port
 */
#define IXP400_TIMESYNCACC_PLREGS_BOFFSET      \
            (IXP400_TIMESYNCACC_BLPLREG_SIZE * \
             IXP400_TIMESYNCACC_PLREGS_COUNT)

/* Compounded Offsets for each of the Port Level Registers as explained
 * in the NOTE of the above comments
 */
#define IXP400_TIMESYNCACC_CC_OFFSET(portNum)  \
            (IXP400_TIMESYNCACC_CC_VOFFSET +   \
             IXP400_TIMESYNCACC_PLREGS_BOFFSET * (portNum))
#define IXP400_TIMESYNCACC_CE_OFFSET(portNum)  \
            (IXP400_TIMESYNCACC_CE_VOFFSET +   \
             IXP400_TIMESYNCACC_PLREGS_BOFFSET * (portNum))
#define IXP400_TIMESYNCACC_XSL_OFFSET(portNum) \
            (IXP400_TIMESYNCACC_XSL_VOFFSET +  \
             IXP400_TIMESYNCACC_PLREGS_BOFFSET * (portNum))
#define IXP400_TIMESYNCACC_XSH_OFFSET(portNum) \
            (IXP400_TIMESYNCACC_XSH_VOFFSET +  \
             IXP400_TIMESYNCACC_PLREGS_BOFFSET * (portNum))
#define IXP400_TIMESYNCACC_RSL_OFFSET(portNum) \
            (IXP400_TIMESYNCACC_RSL_VOFFSET +  \
             IXP400_TIMESYNCACC_PLREGS_BOFFSET * (portNum))
#define IXP400_TIMESYNCACC_RSH_OFFSET(portNum) \
            (IXP400_TIMESYNCACC_RSH_VOFFSET +  \
             IXP400_TIMESYNCACC_PLREGS_BOFFSET * (portNum))
#define IXP400_TIMESYNCACC_UID_OFFSET(portNum) \
            (IXP400_TIMESYNCACC_UID_VOFFSET +  \
             IXP400_TIMESYNCACC_PLREGS_BOFFSET * (portNum))
#define IXP400_TIMESYNCACC_SID_OFFSET(portNum) \
            (IXP400_TIMESYNCACC_SID_VOFFSET +  \
             IXP400_TIMESYNCACC_PLREGS_BOFFSET * (portNum))

/* 
 * Bit Masks of Block Level Control Register
 */
/* Auxiliary Master Mode snapshot Interrupt Mask */
#define IXP400_TIMESYNCACC_TSC_AMMS_MASK    (1 << 3)
/* Auxiliary Slave Mode snapshot Interrupt Mask */
#define IXP400_TIMESYNCACC_TSC_ASMS_MASK    (1 << 2)
/* Target Time Interrupt Mask */
#define IXP400_TIMESYNCACC_TSC_TTM_MASK     (1 << 1)
/* Hardware Assist Reset */
#define IXP400_TIMESYNCACC_TSC_RESET        (1 << 0)

/*
 * Bit Masks of Block Level Event Register
 */
/* Auxiliary Master Mode snapshot Event */
#define IXP400_TIMESYNCACC_TSE_SNM          (1 << 3)
/* Auxiliary Slave Mode snapshot Event */
#define IXP400_TIMESYNCACC_TSE_SNS          (1 << 2)
/* Target Time Interrupt Pending Event */
#define IXP400_TIMESYNCACC_TSE_TTIPEND      (1 << 1)

/*
 * Bit Masks of Channel/Port Level Control Register
 */
/* Timestamp All Messages Control Flag */
#define IXP400_TIMESYNCACC_CC_TA            (1 << 1)
/* Timestamp Master or Slave Mode Control Flag */
#define IXP400_TIMESYNCACC_CC_MM            (1 << 0)

/*
 * Bit Masks of Channel/Port Level Event Register
 */
/* Receive Snapshot Locked Indicator Flag */
#define IXP400_TIMESYNCACC_CE_RXS           (1 << 1)
/* Transmit Snapshot Locked Indicator Flag */
#define IXP400_TIMESYNCACC_CE_TXS           (1 << 0)

/* TimeSync Init Check Macro */
#define IXP400_TIMESYNCACC_INIT_CHECK() \
do { \
    if (FALSE == ixTs1588HardwareAssistEnabled) \
    { \
        /* \
         * Check for IXP46X device NPEs fused-out condition \
         * and Initialise Mem Map \
         */ \
        IxTimeSyncAccInitStatus initStatus = ixTimeSyncAccInitCheck(); \
        if (IX_SUCCESS != (IX_STATUS) initStatus) \
        { \
            ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, \
                "ixTimeSyncAccInitCheck(): TimeSync Initialisation Failed (%x)\n", \
                initStatus,   \
                0,0,0,0,0); \
            return IX_TIMESYNCACC_FAILED; \
        } /* end of if (IX_SUCCESS != (IX_STATUS) initStatus) */ \
    } /* end of if (FALSE == ixTs1588HardwareAssistEnabled) */ \
} while (0) /* Don't include ';' here */

/* NPE Fused-Out Status Check Macro */
#define IXP400_TIMESYNCACC_NPE_FUSED_STATUS_CHECK(ptpPort) \
do { \
    /* Check NPEs Fused-Out status */ \
    if (TRUE != ixTsNpeEnabled[(ptpPort)]) \
{ \
        return IX_TIMESYNCACC_FAILED; \
    } /* end of if (TRUE == ixTsNpeEnabled[(ptpPort)]) */ \
} while (0) /* Don't include ';' here */

/*