ixatmddefines_p.h

有关ARM开发板上的IXP400网络驱动程序的源码以。

* @note - Let the user to specify the size of the pdus he is likely to
*        receive
*
* @note - For now we use a magic number (inherited from PRD requirements
*
*/
#define IX_ATMDACC_MAX_PDU_LEN (65568)

/**
*
* @def IX_ATMDACC_AVERAGE_MBUF_PER_PDU
*
* @brief Maximum number of mbufs in a pdu
*/
#define IX_ATMDACC_AVERAGE_MBUF_PER_PDU \
    (1 + (IX_ATMDACC_MAX_PDU_LEN / IX_ATMDACC_AVERAGE_MBUF_LEN))

/**
*
* @def IX_ATMDACC_MAX_RX_PDU_PENDING
*
* @brief Number of pdu pending in a rx channel
*
* @note - Let the user to specify the number of rx PDUs that
*        are alive in Atmd at any time, this depends on traffic rate
*        queue sizes, and frequency of pdu submit, scheduling, and
*        rx queue processing
*
* @note - For now we use a magic number.dereived from test tuning
*/
#define IX_ATMDACC_MAX_RX_PDU_PENDING 2

/**
*
* @def IX_ATMDACC_RX_NUMBER_OF_DESCRIPTORS
*
* @brief Number of descriptor required per Rx vc
*
* @note - Let the user to specify the number of tx PDUs that
*        are alive in Atmd at any time, this depends on traffic rate
*        queue sizes, and frequency of pdu submit, scheduling, and
*        tx done queue processing.
*
*/
#define IX_ATMDACC_RX_NUMBER_OF_DESCRIPTORS \
    (IX_ATMDACC_MAX_RX_PDU_PENDING * IX_ATMDACC_AVERAGE_MBUF_PER_PDU)

/**
*
* @def IX_ATMDACC_RX_SWQ_SIZE
*
* @brief sw queue size
*
* This evaluation of the sw queue size is done to detect
* bad parameters settings at compile time
*
*/
#define IX_ATMDACC_RX_SWQ_SIZE \
    (IX_ATMDACC_RX_NUMBER_OF_DESCRIPTORS + IX_ATMDACC_AVERAGE_RXFREE_QUEUE_SIZE)

#if IX_ATMDACC_RX_SWQ_SIZE <= 2
#undef IX_ATMDACC_RX_SWQ_SIZE
#define IX_ATMDACC_RX_SWQ_SIZE 2
#else
#if IX_ATMDACC_RX_SWQ_SIZE <= 4
#undef IX_ATMDACC_RX_SWQ_SIZE
#define IX_ATMDACC_RX_SWQ_SIZE 4
#else
#if IX_ATMDACC_RX_SWQ_SIZE <= 8
#undef IX_ATMDACC_RX_SWQ_SIZE
#define IX_ATMDACC_RX_SWQ_SIZE 8
#else
#if IX_ATMDACC_RX_SWQ_SIZE <= 16
#undef IX_ATMDACC_RX_SWQ_SIZE
#define IX_ATMDACC_RX_SWQ_SIZE 16
#else
#if IX_ATMDACC_RX_SWQ_SIZE <= 32
#undef IX_ATMDACC_RX_SWQ_SIZE
#define IX_ATMDACC_RX_SWQ_SIZE 32
#else
#if IX_ATMDACC_RX_SWQ_SIZE <= 64
#undef IX_ATMDACC_RX_SWQ_SIZE
#define IX_ATMDACC_RX_SWQ_SIZE 64
#else
#if IX_ATMDACC_RX_SWQ_SIZE <= 128
#undef IX_ATMDACC_RX_SWQ_SIZE
#define IX_ATMDACC_RX_SWQ_SIZE 128
#else
#if IX_ATMDACC_RX_SWQ_SIZE <= 256
#undef IX_ATMDACC_RX_SWQ_SIZE
#define IX_ATMDACC_RX_SWQ_SIZE 256
#else
#if IX_ATMDACC_RX_SWQ_SIZE <= 512
#undef IX_ATMDACC_RX_SWQ_SIZE
#define IX_ATMDACC_RX_SWQ_SIZE 512
#else
#if IX_ATMDACC_RX_SWQ_SIZE <= 1024
#undef IX_ATMDACC_RX_SWQ_SIZE
#define IX_ATMDACC_RX_SWQ_SIZE 1024
#else
/* the number of descriptor per rx channel exceed a limit
* (The npe cannot chain more than 255 mbufs)
*
* the solution is to reduce the size of the biggest PDU
* or increase the size of the average mbufs. or decrease
* the number of PDU outstanding
*
* see
* IX_ATMDACC_MAX_PDU_LEN
* IX_ATMDACC_AVERAGE_MBUF_LEN
* IX_ATMDACC_MAX_RX_PDU_PENDING
*
*/
#error "Cannot handle so many descriptors per RX channel"

#endif
#endif
#endif
#endif
#endif
#endif
#endif
#endif
#endif
#endif

#if IX_ATMDACC_RX_SWQ_SIZE > IX_NPE_A_CHAIN_DESC_COUNT_MAX
/* the number of descriptor per rx channel exceed a limit
* (The npe cannot chain more than 255 mbufs)
*
* the solution is to reduce the size of the biggest PDU
* or increase the size of the average mbufs. or decrease
* the number of PDU outstanding
*
* see
* IX_ATMDACC_MAX_PDU_LEN
* IX_ATMDACC_AVERAGE_MBUF_LEN
* IX_ATMDACC_MAX_RX_PDU_PENDING
*
*/
#error "Cannot handle so many descriptors per RX channel"

#endif

/**
*
* @def IX_ATMDACC_MAX_TX_PDU_PENDING
*
* @brief Number of pdu pending in a tx channel
*
* @note - Let the user to specify the number of rx PDUs that
*        are alive in Atmd at any time, this depends on traffic rate
*        queue sizes, and frequency of pdu submit, scheduling, and
*        tx done queue processing
*
* @note - For now we use a magic number.dereived from test tuning
*/
#define IX_ATMDACC_MAX_TX_PDU_PENDING 16

/**
*
* @def IX_ATMDACC_AVERAGE_TXVC_QUEUE_SIZE
*
* @brief Average size of a Tx Vc queue
*/
#ifdef IX_NPE_MPHYMULTIPORT
#define IX_ATMDACC_AVERAGE_TXVC_QUEUE_SIZE \
    ((IX_ATMDACC_TXQUEUE0_SIZE + \
    IX_ATMDACC_TXQUEUE1_SIZE + \
    IX_ATMDACC_TXQUEUE2_SIZE + \
    IX_ATMDACC_TXQUEUE3_SIZE + \
    IX_ATMDACC_TXQUEUE4_SIZE + \
    IX_ATMDACC_TXQUEUE5_SIZE + \
    IX_ATMDACC_TXQUEUE6_SIZE + \
    IX_ATMDACC_TXQUEUE7_SIZE + \
    IX_ATMDACC_TXQUEUE8_SIZE + \
    IX_ATMDACC_TXQUEUE9_SIZE + \
    IX_ATMDACC_TXQUEUE10_SIZE + \
    IX_ATMDACC_TXQUEUE11_SIZE) / 12)
#else
#define IX_ATMDACC_AVERAGE_TXVC_QUEUE_SIZE \
    (IX_ATMDACC_TXQUEUE0_SIZE)
#endif /* IX_NPE_MPHY */

/**
*
* @def IX_ATMDACC_TX_NUMBER_OF_DESCRIPTORS
*
* @brief Number of descriptor per tx vc
*
* @note - Let the user to specify the number of tx PDUs that
*        are alive in Atmd at any time, this depends on traffic rate
*        queue sizes, and frequency of pdu submit, scheduling, and
*        tx done queue processing.
*
* @note - For now we use a magic number. It could be twice the size
*       of the tx vc queue
*/
#define IX_ATMDACC_TX_NUMBER_OF_DESCRIPTORS \
    IX_ATMDACC_MAX_TX_PDU_PENDING

/**
*
* @def IX_ATMDACC_TX_SWQ_SIZE
*
* @brief sw queue size
*
* This evaluation of the sw queue size is done to detect
* bad parameters settings at compile time
*
*/
#define IX_ATMDACC_TX_SWQ_SIZE \
    (IX_ATMDACC_TX_NUMBER_OF_DESCRIPTORS + IX_ATMDACC_AVERAGE_TXVC_QUEUE_SIZE)

#if IX_ATMDACC_TX_SWQ_SIZE < IX_ATMDACC_TXDONE_QUEUE_SIZE
#undef IX_ATMDACC_TX_SWQ_SIZE
#define IX_ATMDACC_TX_SWQ_SIZE IX_ATMDACC_TXDONE_QUEUE_SIZE
#endif

#if IX_ATMDACC_TX_SWQ_SIZE <= 2
#undef IX_ATMDACC_TX_SWQ_SIZE
#define IX_ATMDACC_TX_SWQ_SIZE 2
#else
#if IX_ATMDACC_TX_SWQ_SIZE <= 4
#undef IX_ATMDACC_TX_SWQ_SIZE
#define IX_ATMDACC_TX_SWQ_SIZE 4
#else
#if IX_ATMDACC_TX_SWQ_SIZE <= 8
#undef IX_ATMDACC_TX_SWQ_SIZE
#define IX_ATMDACC_TX_SWQ_SIZE 8
#else
#if IX_ATMDACC_TX_SWQ_SIZE <= 16
#undef IX_ATMDACC_TX_SWQ_SIZE
#define IX_ATMDACC_TX_SWQ_SIZE 16
#else
#if IX_ATMDACC_TX_SWQ_SIZE <= 32
#undef IX_ATMDACC_TX_SWQ_SIZE
#define IX_ATMDACC_TX_SWQ_SIZE 32
#else
#if IX_ATMDACC_TX_SWQ_SIZE <= 64
#undef IX_ATMDACC_TX_SWQ_SIZE
#define IX_ATMDACC_TX_SWQ_SIZE 64
#else
#if IX_ATMDACC_TX_SWQ_SIZE <= 128
#undef IX_ATMDACC_TX_SWQ_SIZE
#define IX_ATMDACC_TX_SWQ_SIZE 128
#else
#if IX_ATMDACC_TX_SWQ_SIZE <= 256
#undef IX_ATMDACC_TX_SWQ_SIZE
#define IX_ATMDACC_TX_SWQ_SIZE 256
#else
#if IX_ATMDACC_TX_SWQ_SIZE <= 512
#undef IX_ATMDACC_TX_SWQ_SIZE
#define IX_ATMDACC_TX_SWQ_SIZE 512
#else
#if IX_ATMDACC_TX_SWQ_SIZE <= 1024
#undef IX_ATMDACC_TX_SWQ_SIZE
#define IX_ATMDACC_TX_SWQ_SIZE 1024
#else
/* the number of descriptor per tx channel exceed a limit
* (The npe cannot chain more than 255 mbufs)
*
* the solutiopn is to reduce the number of tx PDU outstanding
*
* IX_ATMDACC_MAX_TX_PDU_PENDING
*
*/
#error "Cannot handle so many descriptors per TX channel"

#endif
#endif
#endif
#endif
#endif
#endif
#endif
#endif
#endif
#endif

#if IX_ATMDACC_TX_SWQ_SIZE > IX_NPE_A_CHAIN_DESC_COUNT_MAX
/* the number of descriptor per tx channel exceed a limit
* (The npe cannot chain more than 255 mbufs)
*
* the solutiopn is to reduce the number of tx PDU outstanding
*
* see IX_ATMDACC_MAX_TX_PDU_PENDING
*
*/
#error "Cannot handle so many descriptors per TX channel"

#endif


/**
*
* @def IX_ATMDACC_TX_OAM_SWQ_SIZE
*
* @brief sw OAM queue size
*
* This defines the maximum number of OAM PDUs
* that may be waiting transmission on a
* port at any time.
*/
#define IX_ATMDACC_TX_OAM_SWQ_SIZE 8

/**
*
* @def IX_ATMDACC_MAX_NPE_DESCRIPTORS
*
* @brief Total number of descriptors required in the system
*
* This number estimates the number of descriptors required
* at any time. This is based on
* @li the average tx queue size
* @li the users's requirements in term of pdu sizes and mbuf sizes
* @li the sw queue characteristics
*
*/

#define IX_ATMDACC_MAX_NPE_DESCRIPTORS \
    ((IX_ATMDACC_RX_SWQ_SIZE     * IX_ATM_MAX_NUM_AAL_VCS) + \
     (IX_ATMDACC_TX_SWQ_SIZE     * IX_ATM_MAX_NUM_AAL_VCS) + \
     (IX_ATMDACC_RX_OAM_SWQ_SIZE * IX_ATM_MAX_NUM_OAM_RX_VCS) + \
     (IX_ATMDACC_TX_OAM_SWQ_SIZE * IX_ATM_MAX_NUM_OAM_TX_VCS))

/**
*
* @def IX_ATMDACC_SWQ_MAX_ENTRIES
*
* @brief Number of entries in a s/w queue
*
* @note Let the user to specify max the number of entries that a s/w queue
*       may hold. This is used only to check that requested queue sizes
*       are below this limit.
*
* @note For now we use a magic number, in reality requested queue sizes will
*       be much less than this.
*/
#define IX_ATMDACC_SWQ_MAX_ENTRIES 1024

/**
*
* @def IX_ATMDACC_QMGR_MAX_QUEUE_SIZE
*
* @brief Maximum size of a QMgr queue
*/
#define IX_ATMDACC_QMGR_MAX_QUEUE_SIZE 128

/**
*
* @def IX_ATMDACC_QMGR_OAM_FREE_QUEUE_SIZE
*
* @brief Maximum size of a QMgr queue for OAM Rx free
*/
#define IX_ATMDACC_QMGR_OAM_FREE_QUEUE_SIZE 16

/**
*
* @def IX_ATMDACC_RX_OAM_SWQ_SIZE
*
* @brief sw OAM queue size
* This defines the maximum number of OAM PDUs
* that may be queued awaiting rx handling at any time.
*
* Following the assumption that the maximum possible
* is defined by the size of the rx queue, the size of the
* rx free queue, and 1 pdu in transit in the NPE.
*
* For symetry some attempt is made to relate the size to the
* size of the transmit channels, anticipating OAM loopback.
* However this dimension only takes effect if atmd is configured
* such that the total transmit capacity is less that the maximum
* OAM receive capacity.
*/
#define IX_ATMDACC_MAX_OAM_RX_POSSIBLE \
( IX_ATMDACC_RX_QUEUE_SIZE + \
  IX_ATMDACC_QMGR_OAM_FREE_QUEUE_SIZE + 1)

#define IX_ATMDACC_MAX_OAM_RX_REQUIRED \
(IX_ATMDACC_TX_OAM_SWQ_SIZE * IX_ATM_MAX_NUM_AAL_VCS )

#if (IX_ATMDACC_MAX_OAM_RX_REQUIRED < IX_ATMDACC_MAX_OAM_RX_POSSIBLE)
#define  IX_ATMDACC_RX_OAM_SWQ_SIZE IX_ATMDACC_MAX_OAM_RX_REQUIRED
#else
#define IX_ATMDACC_RX_OAM_SWQ_SIZE IX_ATMDACC_MAX_OAM_RX_POSSIBLE
#endif


/**
 * @def IX_ATMDACC_AAL0_RX_TIMEOUT [ 0 - 255 ]
 *
 *
 * @brief The time in milliseconds during which received AAL0 cells
 * are accumulated into a PDU. An OAM PDU will be passed to the client
 * either when, the rx mbuf is filled or when this timer expires.
 * A value of 0 disables the timer.
 * The timer resolution is 1ms (a value of 1 results in an
 * expiry in the range 0 - 1 ms).
 */
#define IX_ATMDACC_AAL0_RX_TIMEOUT 4 /* with 2K mbufs  timeout will occur if
                                        the rate falls below 4 Mbits/s */





#endif /* IXATMDDEFINES_P_H */