ixatmddefines_p.h

有关ARM开发板上的IXP400网络驱动程序的源码以。

/**
 * @file IxAtmdDefines_p.h
 *
 * @author Intel Corporation
 * @date 17 March 2002
 *
 * @brief IxAtmdAcc Defines and tunable onstants
 *
 * This header contains the parameters used to configure atmd
 *
 * 
 * @par
 * IXP400 SW Release version 2.1
 * 
 * -- Copyright Notice --
 * 
 * @par
 * Copyright (c) 2001-2005, Intel Corporation.
 * All rights reserved.
 * 
 * @par
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 
 * 
 * @par
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * 
 * @par
 * -- End of Copyright Notice --
 */

#ifndef IXATMDDEFINES_P_H
#define IXATMDDEFINES_P_H

#include "IxAtmTypes.h"
#include "IxNpeA.h"
#include "IxOsal.h"
#include "IxQMgr.h"
#include "IxAtmdAssert_p.h"

#ifdef __vxworks

/* enable function inlining for performances */
#define INLINE __inline__

#else
#ifdef __linux

/* enable function inlining for performances */
#define INLINE __inline__

#else

/* disable function inlining */
#undef INLINE
#define INLINE  /* nothing */

#endif
#endif

/**
*
* @def IX_ATMDACC_PARAM_CHECK
*
* @brief Disable the parameters checking in IxAtmdAcc.
*
* This macro is used to control the input parameter checks in Atmd
* (checking parameters has a significant impact on datapath
* performances). This macro will improve performances
* but increase the risk of errors when using the datapath
* interface during development time.
*/
#ifndef NDEBUG
#define IX_ATMDACC_PARAMS_CHECK( statements ) statements
#else
#if(CPU==SIMSPARCSOLARIS)
/* This is to make sure unit test will pass */
#define IX_ATMDACC_PARAMS_CHECK( statements ) statements
#else
#define IX_ATMDACC_PARAMS_CHECK(x)
#endif
#endif

/**
*
* @def IX_ATMDACC_FULL_STATS
*
* @brief Execute statements if NDEBUG not defined.
*
*/
#ifndef NDEBUG
#define IX_ATMDACC_FULL_STATS(statements) statements
#else
#define IX_ATMDACC_FULL_STATS(x)
#endif

/**
*
* @def IX_ATMD_DEBUG_DO
*
* @brief Execute statements if NDEBUG not defined
*
*/
#ifndef NDEBUG
#define IX_ATMD_DEBUG_DO(statements) statements
#else
#define IX_ATMD_DEBUG_DO(x)
#endif



/* ------------------------------------------------------
*  memory data processing (depending on endianness on xscale)
*
* @note These macros can be empty if no conversion is needed
*       and this improve code efficiency and remove compiler
*       warnings about dead code
* -------------------------------------------------------
*/

/**
*
* @def IX_ATMDACC_CONVERT_TO_BIG_ENDIAN
*
* @brief Conversion of a word to big endian, if needed
*
* @note - If the size of an element is not a word, the
*       actual xscale-npe interface has a specific behaviour
*       by which it is necessary to take care about byte ordering
*
* @sa IX_ATMDACC_CONVERT_FROM_BIG_ENDIAN
*/
#define IX_ATMDACC_CONVERT_TO_BIG_ENDIAN(data32Type, data)  \
     (data) = (data32Type) IX_OSAL_SWAP_BE_SHARED_LONG((UINT32) (data))

#define IX_ATMDACC_CONVERT_TO_BIG_ENDIAN16(data)  \
     (data) = (UINT16) IX_OSAL_SWAP_BE_SHARED_SHORT((UINT16) (data))


/**
*
* @def IX_ATMDACC_CONVERT_FROM_BIG_ENDIAN
*
* @brief Conversion of a word from big endian format, if needed
*
* @note - If the size of an element is not a word, the
*       actual xscale-npe interface has a specific behaviour
*       by which it is necessary to take care about byte ordering
*
* @sa IX_ATMDACC_CONVERT_FROM_BIG_ENDIAN
*/
#define IX_ATMDACC_CONVERT_FROM_BIG_ENDIAN(data32Type, data)  \
     (data) = (data32Type) IX_OSAL_SWAP_BE_SHARED_LONG((UINT32) (data))

#define IX_ATMDACC_CONVERT_FROM_BIG_ENDIAN16(data)  \
     (data) = (UINT16) IX_OSAL_SWAP_BE_SHARED_SHORT((UINT16) (data))



/**
*
* @def IX_ATMDACC_CONVERT_TO_PHYSICAL_ADDRESS
*
* @brief Conversion of a virtaul memory address to a
*        physical memory address (npe use physical memeory
*        address)
*
* @note - if no conversion has to apply, define this macro
*        as empty
*
* @sa IX_ATMDACC_CONVERT_TO_VIRTUAL_ADDRESS
*/
#define IX_ATMDACC_CONVERT_TO_PHYSICAL_ADDRESS(data) \
    do { \
    IX_ATMDACC_ENSURE(*((UINT32 *)(data)) >= 0, "force dereference of valid pointer"); \
    (data) = (void *)IX_OSAL_MMU_VIRT_TO_PHYS((UINT32)data); } while(0)


/**
*
* @def IX_ATMDACC_CONVERT_TO_VIRTUAL_ADDRESS
*
* @brief Conversion of a physical memory address to a
*        virtual memory address (npe use physical memeory
*        address)
*
* @note - if no conversion has to apply, define this macro
*        as empty
*
* @sa IX_ATMDACC_CONVERT_TO_PHYSICAL_ADDRESS
*/
#define IX_ATMDACC_CONVERT_TO_VIRTUAL_ADDRESS(data) \
    do { \
    (data) = (void *)IX_OSAL_MMU_PHYS_TO_VIRT((UINT32)data); \
    IX_ATMDACC_ENSURE(*((UINT32 *)(data)) >= 0, "force dereference of valid pointer"); \
    } while (0)

/**
*
* @def IX_ATMDACC_DATA_CACHE_INVALIDATE
*
* @brief Invalidate the xscale cache: next read access
*        to memory will be done from
*
* @note - if no cache has to apply, define this macro
*        as empty
*
* @sa IX_ATMDACC_DATA_CACHE_FLUSH
*/
#define IX_ATMDACC_DATA_CACHE_INVALIDATE(data,size) \
    do { \
    IX_ATMDACC_ENSURE((data) != NULL, "null pointer passed to IX_OSAL_CACHE_INVALIDATE"); \
    IX_ATMDACC_ENSURE(*((UINT32 *)(data)) >= 0, "force dereference of valid pointer"); \
    IX_ATMDACC_ENSURE((size) > 0, "0 size passed to IX_OSAL_CACHE_INVALIDATE"); \
    IX_OSAL_CACHE_INVALIDATE((UINT32)(data),(size)); } while (0)

/**
*
* @def IX_ATMDACC_DATA_CACHE_FLUSH
*
* @brief Flush the xscale cache.to physical memory
*
* @note - if no flush has to apply, define this macro
*        as empty
*
* @sa IX_ATMDACC_DATA_CACHE_INVALIDATE
*/
#define IX_ATMDACC_DATA_CACHE_FLUSH(data,size) \
    do { \
    IX_ATMDACC_ENSURE((data) != NULL, "null pointer passed to IX_OSAL_CACHE_FLUSH"); \
    IX_ATMDACC_ENSURE(*((UINT32 *)(data)) >= 0, "force dereference of valid pointer"); \
    IX_ATMDACC_ENSURE((size) > 0, "0 size passed to IX_OSAL_CACHE_FLUSH"); \
    IX_OSAL_CACHE_FLUSH((UINT32)(data),(size)); } while (0)



/* -------------------------------------------------------
* Queue tuning
* --------------------------------------------------------
*/

/**
* @def IX_ATMDACC_TXQUEUE0_SIZE
* @brief Size of the tx queue for port 0
*/
#define IX_ATMDACC_TXQUEUE0_SIZE 16

#ifdef IX_NPE_MPHYMULTIPORT

/**
* @def IX_ATMDACC_TXQUEUE1_SIZE
* @brief Size of the tx queue for port 1
*/
#define IX_ATMDACC_TXQUEUE1_SIZE 16

/**
* @def IX_ATMDACC_TXQUEUE2_SIZE
* @brief Size of the tx queue for port 2
*/
#define IX_ATMDACC_TXQUEUE2_SIZE 16

/**
* @def IX_ATMDACC_TXQUEUE3_SIZE
* @brief Size of the tx queue for port 3
*/
#define IX_ATMDACC_TXQUEUE3_SIZE 16

/**
* @def IX_ATMDACC_TXQUEUE4_SIZE
* @brief Size of the tx queue for port 4
*/
#define IX_ATMDACC_TXQUEUE4_SIZE 16

/**
* @def IX_ATMDACC_TXQUEUE5_SIZE
* @brief Size of the tx queue for port 5
*/
#define IX_ATMDACC_TXQUEUE5_SIZE 16

/**
* @def IX_ATMDACC_TXQUEUE6_SIZE
* @brief Size of the tx queue for port 6
*/
#define IX_ATMDACC_TXQUEUE6_SIZE 16

/**
* @def IX_ATMDACC_TXQUEUE7_SIZE
* @brief Size of the tx queue for port 7
*/
#define IX_ATMDACC_TXQUEUE7_SIZE 16

/**
* @def IX_ATMDACC_TXQUEUE8_SIZE
* @brief Size of the tx queue for port 8
*/
#define IX_ATMDACC_TXQUEUE8_SIZE 16

/**
* @def IX_ATMDACC_TXQUEUE9_SIZE
* @brief Size of the tx queue for port 9
*/
#define IX_ATMDACC_TXQUEUE9_SIZE 16

/**
* @def IX_ATMDACC_TXQUEUE10_SIZE
* @brief Size of the tx queue for port 10
*/
#define IX_ATMDACC_TXQUEUE10_SIZE 16

/**
* @def IX_ATMDACC_TXQUEUE11_SIZE
* @brief Size of the tx queue for port 11
*/
#define IX_ATMDACC_TXQUEUE11_SIZE 16

#endif /* IX_NPE_MPHYMULTIPORT */

/**
*
* @def IX_ATMDACC_DOUBLE_SIZE_RXFREE_COUNT
*
* @brief Number of Rx Free queues configured with a double size
*
* These queues are more suitable for high rate traffic and reducing the
* interrupt rate.
*
*/
#define IX_ATMDACC_DOUBLE_SIZE_RXFREE_COUNT 0

/**
*
* @def IX_ATMDACC_AVERAGE_RXFREE_QUEUE_SIZE
*
* @brief Average size of a Rx Free queue
*
* This is the average of queues made from 32 entries and
* queues mde from 16 entries. Channel which want to get
* advantages of best queue size can select them using
* the "minimumQueueSize" parameter in @a ixAtmdAccRxVcConnect
*
* @sa ixAtmdAccRxVcConnect
*
*/
#define IX_ATMDACC_AVERAGE_RXFREE_QUEUE_SIZE \
    (((((1 + IX_NPE_A_QMQ_ATM_RXFREE_MAX) - (IX_NPE_A_QMQ_ATM_RXFREE_MIN + IX_ATMDACC_DOUBLE_SIZE_RXFREE_COUNT)) * 16) + \
    (IX_ATMDACC_DOUBLE_SIZE_RXFREE_COUNT * 32)) / \
    (1 + IX_NPE_A_QMQ_ATM_RXFREE_MAX - IX_NPE_A_QMQ_ATM_RXFREE_MIN))

/**
*
* @def IX_ATMDACC_TXDONE_QUEUE_SIZE
*
* @brief Tx Done Queue Size
*/
#define IX_ATMDACC_TXDONE_QUEUE_SIZE 64


/**
*
* @def IX_ATMDACC_RX_QUEUE_SIZE
*
* @brief Rx Queue Size
*/
#define IX_ATMDACC_RX_QUEUE_SIZE     64

/* ------------------------------------------------------
*  Mbuf setup and tuning
* -------------------------------------------------------
*/

/**
*
* @def IX_ATMDACC_AVERAGE_MBUF_LEN
*
* @brief Minimum size of an mbuf
*
* @note - Let the user to specify the size of the mbufs he is likely to
*        use depending on multiple parameters in the client context and
*        implementation
*
* @note - For now we use a magic number (19 cells)
*
*/
#define IX_ATMDACC_AVERAGE_MBUF_LEN (52 * 19)

/**
*
* @def IX_ATMDACC_MAX_PDU_LEN
*
* @brief Maximum size of a pdu
*