ixatmdportmgmt.c

有关ARM开发板上的IXP400网络驱动程序的源码以。

	(utConfig->utRxConfig.reserved_1 << 23) |  
	(utConfig->utRxConfig.rxCellSize << 16) |  
	(utConfig->utRxConfig.rxHashEnbGFC << 15) |  
	(utConfig->utRxConfig.rxPreHash << 14) |  
	(utConfig->utRxConfig.reserved_2 << 13) |  
	(utConfig->utRxConfig.rxAddrRange << 8) |  
	(utConfig->utRxConfig.reserved_3 << 5) |  
	(utConfig->utRxConfig.rxPHYAddr )
        );
        
        configArrPtr[11] = (UINT32)(  
	(utConfig->utRxStatsConfig.vpi << 20) |  
	(utConfig->utRxStatsConfig.vci << 4) |  
	(utConfig->utRxStatsConfig.pti << 1) |  
	(utConfig->utRxStatsConfig.clp )
        );

        configArrPtr[12] = (UINT32)(  
	(utConfig->utRxDefineIdle.vpi << 20) |  
	(utConfig->utRxDefineIdle.vci << 4) |  
	(utConfig->utRxDefineIdle.pti << 1) |  
	(utConfig->utRxDefineIdle.clp )
        );

        configArrPtr[13] = (UINT32)(  
	(utConfig->utRxEnableFields.defineRxIdleGFC << 31) |  
	(utConfig->utRxEnableFields.defineRxIdlePTI << 30) |  
	(utConfig->utRxEnableFields.defineRxIdleCLP << 29) |  
	(utConfig->utRxEnableFields.phyStatsRxEnb << 28) |  
	(utConfig->utRxEnableFields.vcStatsRxEnb << 27) |  
	(utConfig->utRxEnableFields.vcStatsRxGFC << 26) |  
	(utConfig->utRxEnableFields.vcStatsRxPTI << 25) |  
	(utConfig->utRxEnableFields.vcStatsRxCLP << 24) |  
	(utConfig->utRxEnableFields.discardHecErr << 23) |  
	(utConfig->utRxEnableFields.discardParErr << 22) |  
	(utConfig->utRxEnableFields.discardIdle << 21) |  
	(utConfig->utRxEnableFields.enbHecErrCnt << 20) |  
	(utConfig->utRxEnableFields.enbParErrCnt << 19) |  
	(utConfig->utRxEnableFields.enbIdleCellCnt << 18) |  
	(utConfig->utRxEnableFields.enbSizeErrCnt << 17) |  
	(utConfig->utRxEnableFields.enbRxCellCnt << 16) |  
	(utConfig->utRxEnableFields.reserved_1 << 13) |  
	(utConfig->utRxEnableFields.rxCellOvrInt << 12) |  
	(utConfig->utRxEnableFields.invalidHecOvrInt << 11) |  
	(utConfig->utRxEnableFields.invalidParOvrInt << 10) |  
	(utConfig->utRxEnableFields.invalidSizeOvrInt << 9) |  
	(utConfig->utRxEnableFields.rxIdleOvrInt << 8) |  
	(utConfig->utRxEnableFields.reserved_2 << 5) |  
	(utConfig->utRxEnableFields.rxAddrMask )
        );

        configArrPtr[14] = (UINT32)(  
	(utConfig->utRxTransTable0.phy0 << 27) |  
	(utConfig->utRxTransTable0.phy1 << 22) |  
	(utConfig->utRxTransTable0.phy2 << 17) |  
	(utConfig->utRxTransTable0.reserved_1 << 16) |  
	(utConfig->utRxTransTable0.phy3 << 11) |  
	(utConfig->utRxTransTable0.phy4 << 6) |  
	(utConfig->utRxTransTable0.phy5 << 1) |  
	(utConfig->utRxTransTable0.reserved_2 )
        );

        configArrPtr[15] = (UINT32)(  
	(utConfig->utRxTransTable1.phy6 << 27) |  
	(utConfig->utRxTransTable1.phy7 << 22) |  
	(utConfig->utRxTransTable1.phy8 << 17) |  
	(utConfig->utRxTransTable1.reserved_1 << 16) |  
	(utConfig->utRxTransTable1.phy9 << 11) |  
	(utConfig->utRxTransTable1.phy10 << 6) |  
	(utConfig->utRxTransTable1.phy11 << 1) |  
	(utConfig->utRxTransTable1.reserved_2 )
        );

        configArrPtr[16] = (UINT32)(  
	(utConfig->utRxTransTable2.phy12 << 27) |  
	(utConfig->utRxTransTable2.phy13 << 22) |  
	(utConfig->utRxTransTable2.phy14 << 17) |  
	(utConfig->utRxTransTable2.reserved_1 << 16) |  
	(utConfig->utRxTransTable2.phy15 << 11) |  
	(utConfig->utRxTransTable2.phy16 << 6) |  
	(utConfig->utRxTransTable2.phy17 << 1) |  
	(utConfig->utRxTransTable2.reserved_2 )
        );

        configArrPtr[17] = (UINT32)(  
	(utConfig->utRxTransTable3.phy18 << 27) |  
	(utConfig->utRxTransTable3.phy19 << 22) |  
	(utConfig->utRxTransTable3.phy20 << 17) |  
	(utConfig->utRxTransTable3.reserved_1 << 16) |  
	(utConfig->utRxTransTable3.phy21 << 11) |  
	(utConfig->utRxTransTable3.phy22 << 6) |  
	(utConfig->utRxTransTable3.phy23 << 1) |  
	(utConfig->utRxTransTable3.reserved_2 )
        );

        configArrPtr[18] = (UINT32)(  
	(utConfig->utRxTransTable4.phy24 << 27) |  
	(utConfig->utRxTransTable4.phy25 << 22) |  
	(utConfig->utRxTransTable4.phy26 << 17) |  
	(utConfig->utRxTransTable4.reserved_1 << 16) |  
	(utConfig->utRxTransTable4.phy27 << 11) |  
	(utConfig->utRxTransTable4.phy28 << 6) |  
	(utConfig->utRxTransTable4.phy29 << 1) |  
	(utConfig->utRxTransTable4.reserved_2 )
        );

        configArrPtr[19] = (UINT32)(  
	(utConfig->utRxTransTable5.phy30 << 27) |  
	(utConfig->utRxTransTable5.reserved_1 )
        );


        configArrPtr[20] = (UINT32)( 
        (utConfig->utSysConfig.reserved_1 << 30) |
        (utConfig->utSysConfig.txEnbFSM << 29) |
        (utConfig->utSysConfig.rxEnbFSM << 28) |
        (utConfig->utSysConfig.disablePins << 27) |
        (utConfig->utSysConfig.tstLoop << 26) |
        (utConfig->utSysConfig.txReset << 25) |
        (utConfig->utSysConfig.rxReset << 24) |
        (utConfig->utSysConfig.reserved_2) 
        );    

}




/* ----------------------------------------------
*/
PRIVATE IX_STATUS
ixAtmdAccUtopiaConfigWrite (const IxAtmdAccUtopiaConfig *utConfig)
{
    IX_STATUS returnStatus = IX_SUCCESS;
    UINT32 npeWords[sizeof (IxAtmdAccUtopiaConfig) / sizeof (UINT32)];
    int numWords = sizeof (IxAtmdAccUtopiaConfig) / sizeof (UINT32);
    int wordCnt;

    IX_ATMDACC_ENSURE (numWords < 64, "out of bound structure");

    ixAtmdAccUtopiaConfigGenerate(utConfig,  npeWords);

    /* Write one word of the config at a time to NPE-A */
    for (wordCnt = 0;
    (wordCnt < numWords) && (returnStatus == IX_SUCCESS);
    wordCnt++)
    {
        returnStatus = ixAtmdAccUtilNpeMsgSend (IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE,
            wordCnt * sizeof(UINT32),
            npeWords[wordCnt]);
    } /* end of for(wordCnt) */
    return returnStatus;
}

/* ----------------------------------------------
*/
PRIVATE IX_STATUS
ixAtmdAccUtopiaConfigLoad (void)
{
    IX_STATUS returnStatus = IX_SUCCESS;

    returnStatus = ixAtmdAccUtilNpeMsgWithResponseSend
        (IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD,
        NPE_IGNORE,
        NPE_IGNORE,
        ixAtmdAccUtopiaConfigLoadCallback);;

    if (returnStatus == IX_SUCCESS)
    {
        /* Wait for ixAtmdAccUtopiaConfigGetCallback to release */
        IX_ATMDACC_NPE_RESPONSE_LOCK_GET ();
    }

    return returnStatus;
}

/* ----------------------------------------------
*/
PRIVATE void
ixAtmdAccUtopiaConfigLoadCallback (IxNpeMhNpeId npeMhNpeId,
                                   IxNpeMhMessage npeMhMessage)
{
    UINT32 id;
    UINT32 status;

    /* Check NpeId */
    IX_ATMDACC_ENSURE (npeMhNpeId == IX_NPEMH_NPEID_NPEA, "wrong npeMhNpeId");

    /* Check the ID */
    id = npeMhMessage.data[0] & NPE_RESP_ID_MASK;

    IX_ATMDACC_ENSURE (id == NPE_UT_CONFIG_LOAD_EXPECTED_ID, "wrong id");

    /* Check the status */
    status = npeMhMessage.data[0] & NPE_RESP_STATUS_MASK;
    IX_ATMDACC_ENSURE (status == NPE_SUCCESS, "wrong status");

    /* Unblock the config get context */
    IX_ATMDACC_NPE_RESPONSE_LOCK_RELEASE ();
}

/* ----------------------------------------------
*/
PRIVATE IX_STATUS
ixAtmdAccUtopiaStatusUpload (void)
{
    IX_STATUS returnStatus;

    /* Setup message for UtopiaStatus command */
    returnStatus = ixAtmdAccUtilNpeMsgWithResponseSend(
        IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD,
        NPE_IGNORE,
        NPE_IGNORE,
        ixAtmdAccUtopiaStatusUploadCallback);

    if (returnStatus == IX_SUCCESS)
    {
        /* Wait for ixAtmdAccUtopiaConfigGetCallback to release */
        IX_ATMDACC_NPE_RESPONSE_LOCK_GET ();
    }

    return returnStatus;
}

/* ----------------------------------------------
*/
PRIVATE void
ixAtmdAccUtopiaStatusUploadCallback (IxNpeMhNpeId npeMhNpeId,
                                     IxNpeMhMessage npeMhMessage)
{
    UINT32 id;
    UINT32 status;


    /* Check NpeId */
    IX_ATMDACC_ENSURE (npeMhNpeId == IX_NPEMH_NPEID_NPEA, "wrong npeMhNpeId");

    /* Check the ID */
    id = npeMhMessage.data[0] & NPE_RESP_ID_MASK;

    IX_ATMDACC_ENSURE (id == NPE_UT_STATUS_UPLOAD_EXPECTED_ID, "wrong id");

    /* Check the status */
    status = npeMhMessage.data[0] & NPE_RESP_STATUS_MASK;
    IX_ATMDACC_ENSURE (status == NPE_SUCCESS, "wrong status");

    /* Unblock the config get context */
    IX_ATMDACC_NPE_RESPONSE_LOCK_RELEASE ();
}

/* ----------------------------------------------
*/
PRIVATE void
ixAtmdAccNpeStatusReadCallback (IxNpeMhNpeId npeMhNpeId,
                                IxNpeMhMessage npeMhMessage)
{
    UINT32 id;

    /* Check NpeId */
    IX_ATMDACC_ENSURE (npeMhNpeId == IX_NPEMH_NPEID_NPEA, "wrong npeMhNpeId");

    /* Check Id */
    id = npeMhMessage.data[0] & NPE_RESP_ID_MASK;
    IX_ATMDACC_ENSURE (id == NPE_UT_STATUS_READ_EXPECTED_ID, "wrong id");

    npeRespOffsetRead = npeMhMessage.data[0] & NPE_RESP_OFFSET_MASK;
    npeRespWordRead = npeMhMessage.data[1];

    /* Unblock the reading context */
    IX_ATMDACC_NPE_RESPONSE_LOCK_RELEASE ();
}

/* ----------------------------------------------
* This converts the big Endian utopia status
* received by the NPE. Each 32 bit word represents a utopia
* co-processor register. The corresponding fields in the 
* supplied utopia status struct are filled.
* The constants below represent the regsiter and bit offsets for the 
* fields as defined by utopia co-processor hardware.
* These will never change and are used nowhere apart from in 
* this function.
*/
PRIVATE void 
ixAtmdAccNpeStatusGenerate(IxAtmdAccUtopiaStatus *statusStruct,
                          UINT32 *status)
{
    statusStruct->utTxCellCount     = status[0];
    statusStruct->utTxIdleCellCount = status[1];

    /* extract bit fields */
    statusStruct->utTxCellConditionStatus.txFIFO2Underflow =   ((status[2] >> 29) & 1);
    statusStruct->utTxCellConditionStatus.txFIFO1Underflow =   ((status[2] >> 28) & 1);
    statusStruct->utTxCellConditionStatus.txFIFO2Overflow  =   ((status[2] >> 27) & 1);
    statusStruct->utTxCellConditionStatus.txFIFO1Overflow  =   ((status[2] >> 26) & 1);
    statusStruct->utTxCellConditionStatus.txIdleCellCountOvr = ((status[2] >> 25) & 1);
    statusStruct->utTxCellConditionStatus.txCellCountOvr     = ((status[2] >> 24) & 1);
           
    statusStruct->utRxCellCount       = status[3];
    statusStruct->utRxIdleCellCount   = status[4];
    statusStruct->utRxInvalidHECount  = status[5];
    statusStruct->utRxInvalidParCount = status[6];
    statusStruct->utRxInvalidSizeCount = status[7];
    
    /* extract bit fields */
    statusStruct->utRxCellConditionStatus.rxCellCountOvr      = ((status[8] >> 28) & 1); 
    statusStruct->utRxCellConditionStatus.invalidHecCountOvr  = ((status[8] >> 27) & 1); 
    statusStruct->utRxCellConditionStatus.invalidParCountOvr  = ((status[8] >> 26) & 1); 
    statusStruct->utRxCellConditionStatus.invalidSizeCountOvr = ((status[8] >> 25) & 1); 
    statusStruct->utRxCellConditionStatus.rxIdleCountOvr      = ((status[8] >> 24) & 1); 
    statusStruct->utRxCellConditionStatus.rxFIFO2Underflow    = ((status[8] >> 19) & 1); 
    statusStruct->utRxCellConditionStatus.rxFIFO1Underflow    = ((status[8] >> 18) & 1); 
    statusStruct->utRxCellConditionStatus.rxFIFO2Overflow     = ((status[8] >> 17) & 1); 
    statusStruct->utRxCellConditionStatus.rxFIFO1Overflow     = ((status[8] >> 16) & 1); 
}




/* ----------------------------------------------
*/
PRIVATE IX_STATUS
ixAtmdAccUtopiaStatusRead (IxAtmdAccUtopiaStatus *utStatus)
{
    IX_STATUS returnStatus = IX_SUCCESS;
    UINT32  utStatusWords[sizeof(IxAtmdAccUtopiaStatus)/sizeof(UINT32)];
    int numWords = sizeof(IxAtmdAccUtopiaStatus)/sizeof(UINT32);
    int wordCnt;
    UINT32 readOffset;

    IX_ATMDACC_ENSURE (numWords < 64, "out of bound structure");

    ixOsalMemSet (utStatus, 0, sizeof (IxAtmdAccUtopiaStatus));

    /* Read the status table from NPE memory */

    for (wordCnt = 0;
        (wordCnt < numWords) && (returnStatus == IX_SUCCESS);
        wordCnt++)
    {
        /* offset to read */
        readOffset = wordCnt * sizeof(UINT32);
        /* read the word of the status table at this offset */
        returnStatus = ixAtmdAccUtilNpeMsgWithResponseSend(
            IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ,
            readOffset,
            NPE_IGNORE,
            ixAtmdAccNpeStatusReadCallback);

        if (returnStatus == IX_SUCCESS)
        {
            /* Wait for ixAtmdAccNpeReadCallback to release */
            IX_ATMDACC_NPE_RESPONSE_LOCK_GET ();

            /* Check the address matches the address from ixAtmdAccNpeReadCallback */
            IX_ATMDACC_ENSURE (npeRespOffsetRead == readOffset, "Read error");

            /* Copy the word read from NPE memory into the utopia status
            * structure. NOTE: npewordRead is set by ixAtmdAccNpeReadCallback
            */
            utStatusWords[wordCnt] = npeRespWordRead;

        } /* end of if(returnStatus) */
    } /* end of for(wordCnt) */
    ixAtmdAccNpeStatusGenerate(utStatus,utStatusWords); 

    return returnStatus;
}

/* ----------------------------------------------
*/
PRIVATE BOOL
ixAtmdAccUtopiaConfigSetParamsValidate (const IxAtmdAccUtopiaConfig *utConfig)
{
    unsigned int numberOfPortsToConfigure = 0;
    BOOL isValid = TRUE;

    if (utConfig == NULL)
    {
        isValid = FALSE;
    }

    if (isValid)
    {
        /* txAddrRange  = (numberOfPorts - 1) */
        numberOfPortsToConfigure = utConfig->utTxConfig.txAddrRange + 1;

        /* Number of Rx ports must be equal the the number of Tx ports */
        if (numberOfPortsToConfigure != (utConfig->utRxConfig.rxAddrRange + (UINT32)1))
        {
            isValid = FALSE;
        }
    } /* end of if(isValid) */

    if (isValid)
    {
    /* Check the number of TxVc Queues is equal to the number of configured
    * ports
    */
        if (numTxVcQueues < numberOfPortsToConfigure)
        {
            isValid = FALSE;;
        }

        if (isValid)
        {
            /* Check that the number of ports is valid */
            if (numberOfPortsToConfigure > IX_UTOPIA_MAX_PORTS)
            {
                isValid = FALSE;
            }
        } /* end of if(isValid) */
    } /* end of if(isValid) */

    return isValid;
}