ixatmmutopiacfg.c

有关ARM开发板上的IXP400网络驱动程序的源码以。

    if (!phyCfgValidate (numPorts,
			 phyMode,			 
			 portCfgs))
    {
	return IX_FAIL;
    }

    return IX_SUCCESS;
}    

PRIVATE BOOL
phyCfgValidate (unsigned numPorts,		
		IxAtmmPhyMode phyMode,
		IxAtmmPortCfg portCfgs[])
{
    /* MPHY mode */
    if (phyMode == IX_ATMM_MPHY_MODE)
    {
	UINT32 i;
	for (i=0; i<numPorts; i++)
	{
	    /* Validate the PHY address */
	    if ((portCfgs[i].UtopiaTxPhyAddr >= IX_ATMM_UTOPIA_SPHY_ADDR) ||
		(portCfgs[i].UtopiaRxPhyAddr >= IX_ATMM_UTOPIA_SPHY_ADDR))
	    {
		return FALSE;
	    }
	    /* N.B. not checking for PHY address uniqueness */
	}
        return TRUE;	
    }
    else if (phyMode == IX_ATMM_SPHY_MODE)
    {
	/* 
	 * Nothing to check for SPHY mode
	 * N.B: Phy address is ignored for SPHY mode
	 */
	
	return TRUE;
    }
    /* Any other value for phyMode is not allowed */
    return FALSE;
}

PRIVATE void
utopiaConfigCreate (unsigned numPorts,
		    IxAtmmPhyMode phyMode,
		    IxAtmmPortCfg portCfgs[],
		    IxAtmdAccUtopiaConfig *utCfg,
		    IxAtmmUtopiaLoopbackMode loopbackMode)
{
    utopiaTxConfigCreate (numPorts,
			  phyMode,
			  portCfgs,
			  utCfg,
			  loopbackMode);

    utopiaRxConfigCreate (numPorts,
			  phyMode,
			  portCfgs,
			  utCfg,
			  loopbackMode);

    utopiaSysConfigCreate (utCfg);
}

PRIVATE void 
utopiaRxConfigCreate (unsigned numPorts,
		      IxAtmmPhyMode phyMode,
		      IxAtmmPortCfg portCfgs[],
		      IxAtmdAccUtopiaConfig *utCfg,
		      IxAtmmUtopiaLoopbackMode loopbackMode)
{
    /* Rx Config */
    if (loopbackMode == IX_ATMM_UTOPIA_LOOPBACK_ENABLED)
    {
	utCfg->utRxConfig.rxInterface = IX_ATMM_PHY_SLAVE;
    }
    else
    {
	utCfg->utRxConfig.rxInterface = IX_ATMM_ATM_MASTER;
    }
    utCfg->utRxConfig.rxMode = phyMode;

    utCfg->utRxConfig.rxOctet        = IX_ATMM_DISABLE;
    utCfg->utRxConfig.rxParity       = IX_ATMM_DISABLE;
    utCfg->utRxConfig.rxEvenParity   = IX_ATMM_DISABLE;
    utCfg->utRxConfig.rxHEC          = IX_ATMM_ENABLE;
    utCfg->utRxConfig.rxCOSET        = IX_ATMM_ENABLE;
    utCfg->utRxConfig.rxHECpass      = IX_ATMM_DISABLE; 
    utCfg->utRxConfig.reserved_1     = IX_ATMM_DISABLE;
    utCfg->utRxConfig.rxCellSize     = IX_ATMM_RX_CELL_SIZE;
    utCfg->utRxConfig.rxHashEnbGFC   = IX_ATMM_DISABLE;
    utCfg->utRxConfig.rxPreHash      = IX_ATMM_ENABLE;
    utCfg->utRxConfig.reserved_2     = IX_ATMM_DISABLE;
    utCfg->utRxConfig.rxAddrRange    = numPorts - 1;
    utCfg->utRxConfig.reserved_3     = IX_ATMM_DISABLE;
    utCfg->utRxConfig.rxPHYAddr      = IX_ATMM_UT_RX_STATS_CONFIG_PHY_ADDR;

    /* Rx Stats config */
    utCfg->utRxStatsConfig.vpi = IX_ATMM_UT_RX_STATS_CONFIG_VPI;
    utCfg->utRxStatsConfig.vci = IX_ATMM_UT_RX_STATS_CONFIG_VCI;
    utCfg->utRxStatsConfig.pti = IX_ATMM_UT_TX_STATS_CONFIG_PTI;
    utCfg->utRxStatsConfig.clp = IX_ATMM_UT_TX_STATS_CONFIG_CLP;

    /* Rx Idle cell definition */
    utCfg->utRxDefineIdle.vpi = 0;
    utCfg->utRxDefineIdle.vci = 0;
    utCfg->utRxDefineIdle.pti = IX_ATMM_IGNORE;
    utCfg->utRxDefineIdle.clp = IX_ATMM_IGNORE;

    /* Rx Enable fields */
    utCfg->utRxEnableFields.defineRxIdleGFC   = IX_ATMM_IGNORE;
    utCfg->utRxEnableFields.defineRxIdlePTI   = IX_ATMM_IGNORE;
    utCfg->utRxEnableFields.defineRxIdleCLP   = IX_ATMM_IGNORE;
    utCfg->utRxEnableFields.phyStatsRxEnb     = IX_ATMM_DISABLE;
    utCfg->utRxEnableFields.vcStatsRxEnb      = IX_ATMM_DISABLE;
    utCfg->utRxEnableFields.vcStatsRxGFC      = IX_ATMM_IGNORE;
    utCfg->utRxEnableFields.vcStatsRxPTI      = IX_ATMM_IGNORE;
    utCfg->utRxEnableFields.vcStatsRxCLP      = IX_ATMM_IGNORE;
    utCfg->utRxEnableFields.discardHecErr     = IX_ATMM_ENABLE;
    utCfg->utRxEnableFields.discardParErr     = IX_ATMM_DISABLE;
    utCfg->utRxEnableFields.discardIdle       = IX_ATMM_ENABLE;
    utCfg->utRxEnableFields.enbHecErrCnt      = IX_ATMM_ENABLE;
    utCfg->utRxEnableFields.enbParErrCnt      = IX_ATMM_ENABLE;
    utCfg->utRxEnableFields.enbIdleCellCnt    = IX_ATMM_ENABLE;
    utCfg->utRxEnableFields.enbSizeErrCnt     = IX_ATMM_ENABLE;
    utCfg->utRxEnableFields.enbRxCellCnt      = IX_ATMM_ENABLE;
    utCfg->utRxEnableFields.reserved_1        = 0;
    utCfg->utRxEnableFields.rxCellOvrInt      = IX_ATMM_ENABLE;
    utCfg->utRxEnableFields.invalidHecOvrInt  = IX_ATMM_ENABLE;
    utCfg->utRxEnableFields.invalidParOvrInt  = IX_ATMM_ENABLE;
    utCfg->utRxEnableFields.invalidSizeOvrInt = IX_ATMM_ENABLE;
    utCfg->utRxEnableFields.rxIdleOvrInt      = IX_ATMM_ENABLE;
    utCfg->utRxEnableFields.reserved_2        = 0;
    utCfg->utRxEnableFields.rxAddrMask        = 0;
    
    utopiaRxTransTableSetup (numPorts, portCfgs, utCfg);
}

PRIVATE void
utopiaTxConfigCreate (unsigned numPorts,
		      IxAtmmPhyMode phyMode,
		      IxAtmmPortCfg portCfgs[],
		      IxAtmdAccUtopiaConfig *utCfg,
		      IxAtmmUtopiaLoopbackMode loopbackMode)
{
    /* Tx Config */
    utCfg->utTxConfig.reserved_1  = 0;
    utCfg->utTxConfig.txInterface = IX_ATMM_ATM_MASTER; /* ATM Master */
    utCfg->utTxConfig.txMode = phyMode;

    utCfg->utTxConfig.txOctet        = IX_ATMM_DISABLE; /* Cell level handshaking */
    utCfg->utTxConfig.txParity       = IX_ATMM_ENABLE;
    utCfg->utTxConfig.txEvenParity   = IX_ATMM_DISABLE;
    utCfg->utTxConfig.txHEC          = IX_ATMM_ENABLE;
    utCfg->utTxConfig.txCOSET        = IX_ATMM_ENABLE;
    utCfg->utTxConfig.reserved_2     = 0;
    utCfg->utTxConfig.txCellSize     = IX_ATMM_TX_CELL_SIZE;
    utCfg->utTxConfig.reserved_3     = 0;
    utCfg->utTxConfig.txAddrRange    = numPorts - 1;
    utCfg->utTxConfig.reserved_4     = 0;
    utCfg->utTxConfig.txPHYAddr      = IX_ATMM_UT_TX_STATS_CONFIG_PHY_ADDR;
    
    /* Tx Stats config */
    utCfg->utTxStatsConfig.vpi = IX_ATMM_UT_TX_STATS_CONFIG_VPI;
    utCfg->utTxStatsConfig.vci = IX_ATMM_UT_TX_STATS_CONFIG_VCI;
    utCfg->utTxStatsConfig.pti = IX_ATMM_UT_TX_STATS_CONFIG_PTI;
    utCfg->utTxStatsConfig.clp = IX_ATMM_UT_TX_STATS_CONFIG_CLP;

    /* Tx Idle cell */
    utCfg->utTxDefineIdle.vpi  = 0;
    utCfg->utTxDefineIdle.vci  = 0;
    utCfg->utTxDefineIdle.pti  = 0;
    utCfg->utTxDefineIdle.clp  = 0;
    
    /* Tx Enable fields */
    utCfg->utTxEnableFields.defineTxIdleGFC  = IX_ATMM_IGNORE;
    utCfg->utTxEnableFields.defineTxIdlePTI  = IX_ATMM_IGNORE;
    utCfg->utTxEnableFields.defineTxIdleCLP  = IX_ATMM_IGNORE;
    utCfg->utTxEnableFields.phyStatsTxEnb    = IX_ATMM_DISABLE;
    utCfg->utTxEnableFields.vcStatsTxEnb     = IX_ATMM_DISABLE;
    utCfg->utTxEnableFields.vcStatsTxGFC     = IX_ATMM_IGNORE;
    utCfg->utTxEnableFields.vcStatsTxPTI     = IX_ATMM_IGNORE;
    utCfg->utTxEnableFields.vcStatsTxCLP     = IX_ATMM_IGNORE;    
    utCfg->utTxEnableFields.reserved_1       = 0;
    utCfg->utTxEnableFields.txPollStsInt     = IX_ATMM_ENABLE;
    utCfg->utTxEnableFields.txCellOvrInt     = IX_ATMM_ENABLE;
    utCfg->utTxEnableFields.txIdleCellOvrInt = IX_ATMM_ENABLE;
    utCfg->utTxEnableFields.enbIdleCellCnt   = IX_ATMM_ENABLE;
    utCfg->utTxEnableFields.enbTxCellCnt     = IX_ATMM_ENABLE;
    utCfg->utTxEnableFields.reserved_2       = 0;

    utopiaTxTransTableSetup (numPorts, portCfgs, utCfg);
}

PRIVATE void
utopiaSysConfigCreate (IxAtmdAccUtopiaConfig *utCfg)
{
    /* Utopia system configuration */
    utCfg->utSysConfig.reserved_1  = 0;
    utCfg->utSysConfig.txEnbFSM = IX_ATMM_ENABLE;
    utCfg->utSysConfig.rxEnbFSM = IX_ATMM_ENABLE;
    if (ixAtmmLoopbackOn)
    {
	utCfg->utSysConfig.tstLoop = IX_ATMM_ENABLE;
	utCfg->utSysConfig.disablePins = IX_ATMM_ENABLE;
    }
    else
    {
	utCfg->utSysConfig.tstLoop = IX_ATMM_DISABLE;
	utCfg->utSysConfig.disablePins = IX_ATMM_DISABLE;
    }

    utCfg->utSysConfig.txReset     = IX_ATMM_DISABLE;
    utCfg->utSysConfig.rxReset     = IX_ATMM_DISABLE;
    utCfg->utSysConfig.reserved_2  = 0;
}


/* Reset the System Configuration Structure elements */
PRIVATE void
utopiaSysConfigReset (IxAtmdAccUtopiaConfig *utCfg)
{
    /* Utopia system configuration */
    utCfg->utSysConfig.reserved_1  = 0;
    utCfg->utSysConfig.txEnbFSM    = IX_ATMM_DISABLE;
    utCfg->utSysConfig.rxEnbFSM    = IX_ATMM_DISABLE;
    utCfg->utSysConfig.tstLoop     = IX_ATMM_DISABLE;
    utCfg->utSysConfig.disablePins = IX_ATMM_DISABLE;
    utCfg->utSysConfig.txReset     = IX_ATMM_DISABLE;
    utCfg->utSysConfig.rxReset     = IX_ATMM_DISABLE;
    utCfg->utSysConfig.reserved_2  = 0;
}


PRIVATE void
utopiaRxTransTableSetup (unsigned numPorts,
			 IxAtmmPortCfg portCfgs[],
			 IxAtmdAccUtopiaConfig *utCfg)
{
    /* Utopia Rx translation table */
    switch (numPorts)
    {
	/* 
	 * N.B: Each case will fall thru to the next. e.g. for case
	 * IX_ATMM_NUM_PORTS_4 phys 3,2,1,0 will be configured.
	 */
	case IX_ATMM_NUM_PORTS_12:
	    utCfg->utRxTransTable1.phy11     = portCfgs[11].UtopiaRxPhyAddr;
	case IX_ATMM_NUM_PORTS_11:
	    utCfg->utRxTransTable1.phy10     = portCfgs[10].UtopiaRxPhyAddr;
	case IX_ATMM_NUM_PORTS_10:
	    utCfg->utRxTransTable1.phy9      = portCfgs[9].UtopiaRxPhyAddr;
	case IX_ATMM_NUM_PORTS_9:
	    utCfg->utRxTransTable1.phy8      = portCfgs[8].UtopiaRxPhyAddr;
	case IX_ATMM_NUM_PORTS_8:
	    utCfg->utRxTransTable1.phy7      = portCfgs[7].UtopiaRxPhyAddr;
	case IX_ATMM_NUM_PORTS_7:
	    utCfg->utRxTransTable1.phy6      = portCfgs[6].UtopiaRxPhyAddr;
	case IX_ATMM_NUM_PORTS_6:
	    utCfg->utRxTransTable0.phy5      = portCfgs[5].UtopiaRxPhyAddr;
	case IX_ATMM_NUM_PORTS_5:
	    utCfg->utRxTransTable0.phy4      = portCfgs[4].UtopiaRxPhyAddr;
	case IX_ATMM_NUM_PORTS_4:
	    utCfg->utRxTransTable0.phy3      = portCfgs[3].UtopiaRxPhyAddr;
	case IX_ATMM_NUM_PORTS_3:
	    utCfg->utRxTransTable0.phy2      = portCfgs[2].UtopiaRxPhyAddr;
	case IX_ATMM_NUM_PORTS_2:
	    utCfg->utRxTransTable0.phy1      = portCfgs[1].UtopiaRxPhyAddr;
	case IX_ATMM_NUM_PORTS_1:
	    utCfg->utRxTransTable0.phy0      = portCfgs[0].UtopiaRxPhyAddr;
	    break;
	default:
	    /* Cant get here as numPorts is checked outside */
	    break;
    }
}

PRIVATE void
utopiaTxTransTableSetup (unsigned numPorts,
			 IxAtmmPortCfg portCfgs[],
			 IxAtmdAccUtopiaConfig *utCfg)
{
    /* Utopia Tx translation table */
    switch (numPorts)
    {
	/* 
	 * N.B: Each case will fall thru to the next. e.g. for case
	 * IX_ATMM_NUM_PORTS_4 phys 3,2,1,0 will be configured.
	 */
	case IX_ATMM_NUM_PORTS_12:
	    utCfg->utTxTransTable1.phy11     = portCfgs[11].UtopiaTxPhyAddr;
	case IX_ATMM_NUM_PORTS_11:
	    utCfg->utTxTransTable1.phy10     = portCfgs[10].UtopiaTxPhyAddr;
	case IX_ATMM_NUM_PORTS_10:
	    utCfg->utTxTransTable1.phy9      = portCfgs[9].UtopiaTxPhyAddr;
	case IX_ATMM_NUM_PORTS_9:
	    utCfg->utTxTransTable1.phy8      = portCfgs[8].UtopiaTxPhyAddr;
	case IX_ATMM_NUM_PORTS_8:
	    utCfg->utTxTransTable1.phy7      = portCfgs[7].UtopiaTxPhyAddr;
	case IX_ATMM_NUM_PORTS_7:
	    utCfg->utTxTransTable1.phy6      = portCfgs[6].UtopiaTxPhyAddr;
	case IX_ATMM_NUM_PORTS_6:
	    utCfg->utTxTransTable0.phy5      = portCfgs[5].UtopiaTxPhyAddr;
	case IX_ATMM_NUM_PORTS_5:
	    utCfg->utTxTransTable0.phy4      = portCfgs[4].UtopiaTxPhyAddr;
	case IX_ATMM_NUM_PORTS_4:
	    utCfg->utTxTransTable0.phy3      = portCfgs[3].UtopiaTxPhyAddr;
	case IX_ATMM_NUM_PORTS_3:
	    utCfg->utTxTransTable0.phy2      = portCfgs[2].UtopiaTxPhyAddr;
	case IX_ATMM_NUM_PORTS_2:
	    utCfg->utTxTransTable0.phy1      = portCfgs[1].UtopiaTxPhyAddr;
	case IX_ATMM_NUM_PORTS_1:
	    utCfg->utTxTransTable0.phy0      = portCfgs[0].UtopiaTxPhyAddr;
	    break;