ixdmaacc_p.h

有关ARM开发板上的IXP400网络驱动程序的源码以。

*           Binary       00000011 00000000 00000000 00000000
*            Hex              03       00       00      00
*/

#define IX_DMA_MODE_TRANSWIDTH_32_BURST   0x03000000

/*
* @def IX_DMA_MODE_TRANSWIDTH_16_BURST
* @brief Mask for Transfer Width
*        Bit 25,24 Source 16 bits      = 1,0
*        Bit 17,16 Destination Burst   = 0,0
*                       31       23       15        7      0
*                        |-----xx |-----xx |------- |------|
*           Binary       00000010 00000000 00000000 00000000
*            Hex              02       00       00      00
*/
#define IX_DMA_MODE_TRANSWIDTH_16_BURST    0x02000000

/*
* @def IX_DMA_MODE_TRANSWIDTH_8_BURST
* @brief Mask for Transfer Width
*        Bit 25,24 Source 8 bits     = 0,1
*        Bit 17,16 Destination Burst = 0,0
*                       31       23       15        7      0
*                        |-----xx |-----xx |------- |------|
*           Binary       00000001 00000000 00000000 00000000
*            Hex              01       00       00      00
*/
#define IX_DMA_MODE_TRANSWIDTH_8_BURST    0x01000000

/*
* @def IX_DMA_MODE_TRANSWIDTH_BURST_32
* @brief Mask for Transfer Width
*        Bit 25,24 Source Burst        = 0,0
*        Bit 17,16 Destination 32 bits = 1,1
*                       31       23       15        7      0
*                        |-----xx |-----xx |------- |------|
*           Binary       00000000 00000011 00000000 00000000
*            Hex              00       03       00      00
*/
#define IX_DMA_MODE_TRANSWIDTH_BURST_32   0x00030000

/*
* @def IX_DMA_MODE_TRANSWIDTH_BURST_16
* @brief Mask for Transfer Width
*        Bit 25,24 Source Burst        = 0,0
*        Bit 17,16 Destination 16 bits = 1,0
*                       31       23       15        7      0
*                        |-----xx |-----xx |------- |------|
*           Binary       00000000 00000010 00000000 00000000
*            Hex              00       02       00      00
*/
#define IX_DMA_MODE_TRANSWIDTH_BURST_16   0x00020000

/*
* @def IX_DMA_MODE_TRANSWIDTH_BURST_8
* @brief Mask for Transfer Width
*        Bit 25,24 Source Burst      = 0,0
*        Bit 17,16 Destination 8 bits = 0,1
*                       31       23       15        7      0
*                        |-----xx |-----xx |------- |------|
*           Binary       00000000 00000001 00000000 00000000
*            Hex              00       01       00      00
*/
#define IX_DMA_MODE_TRANSWIDTH_BURST_8    0x00010000

/*
* @def IX_DMA_MODE_TRANSWIDTH_BURST_BURST
* @brief Mask for Transfer Width
*        Bit 25,24 Source Burst      = 0,0
*        Bit 17,16 Destination Burst = 0,0
*                       31       23       15        7      0
*                        |-----xx |-----xx |------- |------|
*           Binary       00000000 00000000 00000000 00000000
*            Hex              00       00       00      00
*/
#define IX_DMA_MODE_TRANSWIDTH_BURST_BURST  0x00000000

/**
 * @def IX_DMA_ACC_MEMFREE
 *
 * @brief To free the memory allocated through IX_OSAL_CACHE_DMA_MALLOC 
 *        function.
 *
 * @note Example of usage: IX_DMA_ACC_MEMFREE(pData)
 *
 * @param UINT8 [in] *pData - memory block pointer to be freed.
 *
 */
#ifdef __vxworks

#define IX_DMA_ACC_MEMFREE(pData) cacheDmaFree (pData)

#else

#define IX_DMA_ACC_MEMFREE(pData) (pData) 	  /* Note: Do nothing in
                                                   * Linux platform. Will be
                                                   * ported to Linux platform.
                                                   */
#endif /* def __vxworks */



/**
 * @enum IxDmaReturnStatus
 * @brief Dma return status definitions
 */
typedef enum
{
    IX_DMA_DM_SUCCESS = IX_SUCCESS,  /**< DMA Transfer Success */
    IX_DMA_DM_FAIL = IX_FAIL,        /**< DMA Transfer Fail */
    IX_DMA_DM_FIFO_FULL,             /**< DMA Descriptor Pool FIFO full */
    IX_DMA_DM_FIFO_EMPTY,            /**< DMA Descriptor Pool FIFO empty */
    IX_DMA_DM_INDEX_CORRUPTED        /**< DMA Descriptor Pool Index Corrupted */
} IxDmaDescMgrStatus;

/**
 * @struct IxDmaNpeQDescriptor
 * @brief Structure for storing descriptor parameters
 */
typedef struct {
    UINT32 sourceAddress;      /**< Source address for dma transfer
                                 */
    UINT32 destinationAddress; /**< Destination address for dma transfer
                                 */
    UINT32 operationMode;      /**< Operation mode for dma transfer
                                 */
    IxDmaAccDmaCompleteCallback pDmaCallback;
                               /**< Pointer to client callback for dma transfer
                                 */
} IxDmaNpeQDescriptor;

/**
 * @struct IxDmaDescriptorPool
 * @brief Structure for storing the descriptor pointers
 */
typedef struct {
    IxDmaNpeQDescriptor **pDmaNpeQDescriptor;
                           /**< Pointer to array of descriptors
                             */
    UINT32 size;           /**< Size of descriptor pool
                             */
    UINT32 allocatedCnt;   /**< Counter for descriptors in use
                             */
    UINT32 head;           /**< Ring buffer Index Head
                             */
    UINT32 tail;           /**< Ring buffer Index Tail
                             */
} IxDmaDescriptorPool;

/**
 * @struct  IxDmaAccStats
 * @brief   Data structure for statistics
 *
 */
typedef struct
{
    UINT32 successCnt;        /**< Counter for number of requests
                               * completed successfully
                               */
    UINT32 failCnt;           /**< Counter for number of requests
                               * failed
                               */
    UINT32 qOverflowCnt;      /**< Counter for number of times
                               * queue overflow
                               * (Writing DMA Request Q returns a Fail)
                               */
    UINT32 qUnderflowCnt;     /**< Counter for number of times
                               * queue underflow
                               * (Reading DMA Done Q returns a Fail)
                               */
    UINT32 qDescAddrInvalidCnt; /**< Counter for number of times
                                 * Q descriptor address received
                                 * as NULL value (invalid)
                                 */
} IxDmaAccStats;

/**
 * @brief Allocate and initialize the descriptor pool
 * @param None
 * @return @li IX_SUCCESS Notification that descriptor pool initialization is
 *         @li            succesful
 * @return @li IX_FAIL 	 Error initializing descriptor pool
 */

IX_STATUS
ixDmaAccDescriptorPoolInit (void);


IX_STATUS ixDmaAccDescriptorPoolUninit(void);
/**
 * @brief Return pointer to descriptor entry
 * @param pDescriptor Pointer to descriptor within an array
 * @return @li IX_DMA_DM_SUCCESS Free descriptor pointer succesfully returned
 * @return @li IX_DMA_DM_FAIL Invalid descriptor address
 * @return @li IX_DMA_DM_FIFO_FULL Descriptor get request when FIFO is full
 * @return @li IX_DMA_DM_INDEX_CORRUPTED Index for Desc Pool corrupted
 */
IxDmaDescMgrStatus
ixDmaAccDescriptorGet (IxDmaNpeQDescriptor **pDescriptor);

/**
 * @brief Free the oldest entry in the descriptor pool
 * @param pDescriptor Pointer to descriptor
 * @return @li IX_DMA_DM_SUCCESS Free descriptor pointer succesfully returned
 * @return @li IX_DMA_DM_FAIL Invalid descriptor address
 * @return @li IX_DMA_DM_FIFO_EMPTY Descriptor free request when FIFO is empty
 * @return @li IX_DMA_DM_INDEX_CORRUPTED Index for Desc Pool corrupted
 */

IxDmaDescMgrStatus
ixDmaAccDescriptorFree (IxDmaNpeQDescriptor *pDescriptor);

/**
 * @brief       Validate parameters for DMA transfer
 * This function will validate parameters for DMA transfer.
 *
 * @param ixDmaSourceAddr	    Starting address of DMA source.
 *                              Must be a valid IXP400 memory map address.
 * @param ixDmaDestinationAddr	Starting address of DMA destination.
 *                              Must be a valid IXP400 memory map address.
 * @param ixDmaTransferLength	The size of DMA data transfer.
 *                              The range must be from 1-65535 bytes
 * @param ixDmaTransferMode	    The DMA transfer mode
 * @param ixDmaAddressingMode	The DMA addressing mode
 * @param ixTransferWidth	    The DMA transfer width
 *
 * @return @li IX_DMA_SUCCESS 	Notification that the DMA request is succesful
 * @return @li IX_DMA_FAIL 	    IxDmaAcc not yet initialised or some internal
 *                              error has occured
 * @return @li IX_DMA_INVALID_TRANSFER_WIDTH Transfer width is not valid
 * @return @li IX_DMA_INVALID_TRANSFER_LENGTH Transfer length outside of valid
 *                                            range
 * @return @li IX_DMA_INVALID_TRANSFER_MODE Transfer Mode not valid
 * @return @li IX_DMA_REQUEST_FIFO_FULL IxDmaAcc request queue is full
 */
IxDmaReturnStatus
ixDmaAccParamsValidate(
                        UINT32 SourceAddr,
                        UINT32 DestinationAddr,
                        UINT16 TransferLength,
                        IxDmaTransferMode TransferMode,
                        IxDmaAddressingMode AddressingMode,
                        IxDmaTransferWidth TransferWidth);
/**
 * @brief This callback is registered with the queue manager for
 *        notification of Dma transfer done event
 *        Q manager calls this function when Queue is Not Empty
 * @param qId    Queue Identifier for Dma done
 * @param cbId   Callback Identifier for Dma done
 *
 * @return none
 */
void
ixDmaTransferDoneCallback (IxQMgrQId qId, IxQMgrCallbackId cbId);

/**
 * @brief Show descriptor pool statistics
 * @param None
 * @return None
 */
void
ixDmaAccDescPoolShow (void);

/**
 * @brief Free memory allocated to descriptor pool
 * @param None
 * @return None
 */
void
ixDmaAccDescPoolFree(void);
#endif /* IXDMAACC_P_H */