ixdmaacc.c

有关ARM开发板上的IXP400网络驱动程序的源码以。

    #endif

    /* Select the Queues based on the NPE to be used */
    switch (npeId)
    {
        case IX_NPEDL_NPEID_NPEA:
             /* Select the Queues for NPE A */
             ixDmaQIdDmaDone = IX_DMA_NPE_A_DONE_QID;            /* NPE A Done Q Id    */
             ixDmaQIdDmaRequest = IX_DMA_NPE_A_REQUEST_QID;      /* NPE A Request Q Id */
             break;
        case IX_NPEDL_NPEID_NPEB:
             /* Select the Queues for NPE B */
             ixDmaQIdDmaDone = IX_DMA_NPE_B_DONE_QID;            /* NPE B Done Q Id    */
             ixDmaQIdDmaRequest = IX_DMA_NPE_B_REQUEST_QID;      /* NPE B Request Q Id */
             break;
        case IX_NPEDL_NPEID_NPEC:
             /* Select the Queues for NPE C */
             ixDmaQIdDmaDone = IX_DMA_NPE_C_DONE_QID;            /* NPE C Done Q Id    */
             ixDmaQIdDmaRequest = IX_DMA_NPE_C_REQUEST_QID;      /* NPE C Request Q Id */
             break;
        default:
             /* Invalid NPE ID */
             ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
                        IX_OSAL_LOG_DEV_STDERR,
                        "\n ixDmaAccUninit : invalid Npe ID.",
                        0,0,0,0,0,0);
             return IX_FAIL;
     } /* end of switch (npeId) */

    status = ixQMgrNotificationDisable (ixDmaQIdDmaDone);
	if (IX_SUCCESS != status)
	{
		ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
                   IX_OSAL_LOG_DEV_STDERR,
                   "\n ixDmaAccUninit : ixQMgrNotificationDisable failed.",
                   0,0,0,0,0,0);
	}

    status = ixQMgrNotificationCallbackSet (ixDmaQIdDmaDone, NULL, 0);
	if (IX_SUCCESS != status)
	{
		ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
                   IX_OSAL_LOG_DEV_STDERR,
                   "\n ixDmaAccUninit : ixQMgrNotificationCallbackSet failed.",
                   0,0,0,0,0,0);
	}
    status = ixQMgrNotificationDisable (ixDmaQIdDmaRequest);
	if (IX_SUCCESS != status)
	{
		ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
                   IX_OSAL_LOG_DEV_STDERR,
                   "\n ixDmaAccUninit : ixQMgrNotificationDisable failed.",
                   0,0,0,0,0,0);
	}
    status = ixQMgrNotificationCallbackSet (ixDmaQIdDmaRequest, NULL, 0);
	if (IX_SUCCESS != status)
	{
		ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
                   IX_OSAL_LOG_DEV_STDERR,
                   "\n ixDmaAccUninit : ixQMgrNotificationCallbackSet failed.",
                   0,0,0,0,0,0);
	}

    /* Initialize dma statistics */
    dmaStats.successCnt          = 0;
    dmaStats.failCnt             = 0;
    dmaStats.qOverflowCnt        = 0;
    dmaStats.qUnderflowCnt       = 0;
    dmaStats.qDescAddrInvalidCnt = 0;

    status = ixDmaAccDescriptorPoolUninit ();
	if (IX_SUCCESS != status)
    {
		ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
                   IX_OSAL_LOG_DEV_STDERR,
                   "\n ixDmaAccUninit : ixDmaAccDescriptorPoolUninit failed.",
                   0,0,0,0,0,0);
	}

	ixDmaAccInitDone = FALSE;
    return status;
}



/***********************************************************************
 * @fn ixDmaAccDmaTransfer
 *
 * @param In: ixDmaSourceAddr : Start address of DMA source
 * @param In: ixDmaDestinationAddr : Start address of DMA destination
 * @param In: ixDmaTransferLength : Size of DMA transfer (1-64Kb)
 * @param In: ixDmaTransferMode : DMA transfer mode
 * @param In: ixDmaAddressingMode : DMA addressing mode
 * @param In: ixTransferWidth : DMA transfer width
 * @param Callback : to call when DMA transfer is done
 * @brief Perform the DMA transfer
 *
 * @return IX_DMA_SUCCESS : notification that DMA request is succesful
 * @return IX_DMA_FAIL    : IxDmaAcc not yet initialized or internal error
 * @return IX_DMA_INVALID_TRANSFER_WIDTH : transfer width is not valid
 * @return IX_DMA_INVALID_TRANSFER_LENGTH: length of transfer not valid
 * @return IX_DMA_INVALID_TRANSFER_MODE  : transfer mode not valid
 * @return IX_DMA_INVALID_ADDRESS_MODE   : address mode not valid
 * @return IX_DMA_REQUEST_FIFO_FULL : IxDmaAcc request queue is full
 *
 ***********************************************************************/
PUBLIC IxDmaReturnStatus
ixDmaAccDmaTransfer(
    IxDmaAccDmaCompleteCallback callback,
    UINT32 sourceAddr,
    UINT32 destinationAddr,
    UINT16 transferLength,
    IxDmaTransferMode transferMode,
    IxDmaAddressingMode addressingMode,
    IxDmaTransferWidth transferWidth)
{
    UINT32 operationMode=0;  /* Variable for composing transfer mode is
                                initialized to zero */
    IxDmaReturnStatus dmaStatus;     /* Return status for Dma transfer */
    IxDmaNpeQDescriptor *descriptorPtr; /* Pointer to descriptor */
    UINT32 u32pNpeQDesc = 0;
	/* Check if ixDmaInit has been initialized already*/
    if( FALSE == ixDmaAccInitDone )
    {
        /* Log error message in debugging mode */
        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
        		   IX_OSAL_LOG_DEV_STDERR,
            	   "\nixDmaAccDmaTransfer : transfer called before initialization.",
            	   0,0,0,0,0,0);
        return (IX_DMA_FAIL);
    } /* end of if(!ixDmaAccInitDone) */

    /* Validate parameters provided by the caller : ixDmaAccParamsValidate */
    dmaStatus = ixDmaAccParamsValidate( sourceAddr,
                                        destinationAddr,
                                        transferLength,
                                        transferMode,
                                        addressingMode,
                                        transferWidth);

    if( IX_DMA_SUCCESS != dmaStatus )
    {
        /* Log error message in debugging mode */
        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
        		   IX_OSAL_LOG_DEV_STDERR,
                   "\nixDmaAccDmaTransfer : parameter validation failed.",
                   0,0,0,0,0,0);
        return dmaStatus;
    }  /* end of if(dmaStatus) */

    /* Compose the Addressing Mode field in the DMA Transfer Mode
       descriptor word */
    switch (addressingMode)
    {
        case IX_DMA_INC_SRC_INC_DST:
             /* Compose the Addressing Mode field for src address increment
                and dest address increment */
             operationMode |= IX_DMA_MODE_INC_INC;
             break;
        case IX_DMA_INC_SRC_FIX_DST:
             /* Compose the Addressing Mode field for src address increment
                and fixed dest address */
             operationMode |= IX_DMA_MODE_INC_FIX;
             break;
        case IX_DMA_FIX_SRC_INC_DST:
             /* Compose the Addressing Mode field for fixed src address and
                dest address increment */
             operationMode |= IX_DMA_MODE_FIX_INC;
             break;
        default:
             /* Mode is not valid and should have been rejected at validation
                check */
             return IX_DMA_INVALID_ADDRESS_MODE;
     } /* end of switch (transferMode) */

    /* Compose the Transfer Mode field in the DMA Transfer Mode
       descriptor word */
    switch (transferMode)
    {
        case IX_DMA_COPY:
             /* Compose the Transfer Mode field for copy only */
             operationMode |= IX_DMA_MODE_COPY;
             break;
        case IX_DMA_COPY_CLEAR:
             /* Compose the Transfer Mode field for copy and clear source */
             operationMode |= IX_DMA_MODE_COPY_CLEAR;
             break;
        case IX_DMA_COPY_BYTE_SWAP:
             /* Compose the Transfer Mode field for copy and byte swap */
             operationMode |= IX_DMA_MODE_COPY_BYTE_SWAP;
             break;
        case IX_DMA_COPY_REVERSE:
             /* Compose the Transfer Mode field for copy and byte reverse */
             operationMode |= IX_DMA_MODE_COPY_REVERSE;
             break;
        default:
             /* Mode is not valid and should have been rejected at validation check */
             return IX_DMA_INVALID_TRANSFER_MODE;
     } /* end of switch (transferMode) */

    /* Compose the Transfer Width field in the DMA Transfer Mode descriptor word */
    switch (transferWidth)
    {
        /* Compose the Transfer Width field for 32 bit src and 32 bit dst */
        case IX_DMA_32_SRC_32_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_32_32;
             break;
        /* Compose the Transfer Width field for 32 bit src and 16 bit dst */
        case IX_DMA_32_SRC_16_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_32_16;
             break;
        /* Compose the Transfer Width field for 32 bit src and 8 bit dst */
        case IX_DMA_32_SRC_8_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_32_8;
             break;
        /* Compose the Transfer Width field for 16 bit src and 3 bit dst */
        case IX_DMA_16_SRC_32_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_16_32;
             break;
        /* Compose the Transfer Width field for 16 bit src and 16 bit dst */
        case IX_DMA_16_SRC_16_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_16_16;
             break;
        /* Compose the Transfer Width field for 16 bit src and 8 bit dst */
        case IX_DMA_16_SRC_8_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_16_8;
             break;
        /* Compose the Transfer Width field for 8 bit src and 32 bit dst */
        case IX_DMA_8_SRC_32_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_8_32;
             break;
        /* Compose the Transfer Width field for 8 bit src and 16 bit dst */
        case IX_DMA_8_SRC_16_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_8_16;
             break;
        /* Compose the Transfer Width field for 8 bit src and 8 bit dst */
        case IX_DMA_8_SRC_8_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_8_8;
             break;
        /* Compose the Transfer Width field for 32 bit src and burst dst */
        case IX_DMA_32_SRC_BURST_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_32_BURST;
             break;
        /* Compose the Transfer Width field for 16 bit src and burst dst */
        case IX_DMA_16_SRC_BURST_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_16_BURST;
             break;
        /* Compose the Transfer Width field for 8 bit src and burst dst */
        case IX_DMA_8_SRC_BURST_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_8_BURST;
             break;
        /* Compose the Transfer Width field for burst src and 32 bit dst */
        case IX_DMA_BURST_SRC_32_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_BURST_32;
             break;
        /* Compose the Transfer Width field for burst src and 16 bit dst */
        case IX_DMA_BURST_SRC_16_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_BURST_16;
             break;
        /* Compose the Transfer Width field for burst src and 8 bit dst */
        case IX_DMA_BURST_SRC_8_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_BURST_8;
             break;
        /* Compose the Transfer Width field for burst src and burst dst */
        case IX_DMA_BURST_SRC_BURST_DST:
             operationMode |= IX_DMA_MODE_TRANSWIDTH_BURST_BURST;
             break;
        default:
             /* Mode is not valid and should have been rejected at
                validation check */
        return IX_DMA_INVALID_TRANSFER_WIDTH;
    } /* end of switch (transferWidth) */

    /* Since parameters are valid, get descriptor entry from the descriptor
       manager */
    if( IX_DMA_DM_FIFO_FULL == ixDmaAccDescriptorGet(&descriptorPtr) )
    {
        /* Log error message in debugging mode */
        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
        		   IX_OSAL_LOG_DEV_STDERR,
                   "\nDma transfer aborted : descriptor get failed.",
                   0,0,0,0,0,0);
        return (IX_DMA_REQUEST_FIFO_FULL);
    }  /* end of if(ixDmaAccDescriptorGet) */

    /* Compose the first sixteen bits with tranfer length */
    operationMode |= (UINT32) transferLength;

    /* Load first descriptor word : source address */
    descriptorPtr->sourceAddress = IX_OSAL_MMAP_VIRT_TO_PHYS(sourceAddr); 

    /* Load second descriptor word : destination address */
    descriptorPtr->destinationAddress = IX_OSAL_MMAP_VIRT_TO_PHYS(destinationAddr);

    /* Load third descriptor word : Dma transfer mode */
    descriptorPtr->operationMode = operationMode;

    /* Load third descriptor word : Pointer to callback function */
    descriptorPtr->pDmaCallback = callback;

    /* Flush the cache for descriptor before performing a write to the
       Dma request Q */
    IX_OSAL_CACHE_FLUSH(descriptorPtr,sizeof(IxDmaNpeQDescriptor));

    /* Translate descriptor address from Virtual to Physical */
    descriptorPtr = (IxDmaNpeQDescriptor*)
                    IX_OSAL_MMU_VIRT_TO_PHYS(descriptorPtr);

    /* Load descriptor pointer to the DMA REQUEST Q */
    u32pNpeQDesc = (UINT32)descriptorPtr; 
    if ( IX_SUCCESS !=
         ixQMgrQWrite( ixDmaQIdDmaRequest,
                       &u32pNpeQDesc) )
    {
        /* IX_DMA_REQUEST_FIFO_FULL, increase the counter */
        dmaStats.qOverflowCnt++;
        /* Descriptor failed to load into dma request queue */
        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
        		   IX_OSAL_LOG_DEV_STDERR,
                   "\nDma transfer aborted : dma request Q overflow.",
                   0,0,0,0,0,0);
        return (IX_DMA_REQUEST_FIFO_FULL);
    }  /* end of if (ixQMgrQWrite) */
    /* Increment counter for number of transfer requests completed
     * successfully without error
     */
    dmaStats.successCnt++;